43a44
> #include "arch/riscv/system.hh"
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< if (FullSystem)
< panic("translateInst not implemented in RISC-V.\n");
---
> if (FullSystem) {
> /**
> * check if we simulate a bare metal system
> * if so, we have no tlb, phys addr == virt addr
> */
> if (static_cast<RiscvSystem *>(tc->getSystemPtr())->isBareMetal())
> req->setFlags(Request::PHYSICAL);
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< Process * p = tc->getProcessPtr();
---
> if (req->getFlags() & Request::PHYSICAL) {
> /**
> * we simply set the virtual address to physical address
> */
> req->setPaddr(req->getVaddr());
> return checkCacheability(req);
> } else {
> /**
> * as we currently support bare metal only, we throw a panic,
> * if it is not a bare metal system
> */
> panic("translateInst not implemented in RISC-V.\n");
> }
> } else {
> Process * p = tc->getProcessPtr();
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< Fault fault = p->pTable->translate(req);
< if (fault != NoFault)
< return fault;
---
> Fault fault = p->pTable->translate(req);
> if (fault != NoFault)
> return fault;
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< return NoFault;
---
> return NoFault;
> }
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< if (FullSystem)
< panic("translateData not implemented in RISC-V.\n");
---
> if (FullSystem) {
> /**
> * check if we simulate a bare metal system
> * if so, we have no tlb, phys addr == virt addr
> */
> if (static_cast<RiscvSystem *>(tc->getSystemPtr())->isBareMetal())
> req->setFlags(Request::PHYSICAL);
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< // In the O3 CPU model, sometimes a memory access will be speculatively
< // executed along a branch that will end up not being taken where the
< // address is invalid. In that case, return a fault rather than trying
< // to translate it (which will cause a panic). Since RISC-V allows
< // unaligned memory accesses, this should only happen if the request's
< // length is long enough to wrap around from the end of the memory to the
< // start.
< assert(req->getSize() > 0);
< if (req->getVaddr() + req->getSize() - 1 < req->getVaddr())
< return make_shared<GenericPageTableFault>(req->getVaddr());
---
> if (req->getFlags() & Request::PHYSICAL) {
> /**
> * we simply set the virtual address to physical address
> */
> req->setPaddr(req->getVaddr());
> return checkCacheability(req);
> } else {
> /**
> * as we currently support bare metal only, we throw a panic,
> * if it is not a bare metal system
> */
> panic("translateData not implemented in RISC-V.\n");
> }
> } else {
> // In the O3 CPU model, sometimes a memory access will be speculatively
> // executed along a branch that will end up not being taken where the
> // address is invalid. In that case, return a fault rather than trying
> // to translate it (which will cause a panic). Since RISC-V allows
> // unaligned memory accesses, this should only happen if the request's
> // length is long enough to wrap around from the end of the memory to
> // the start.
> assert(req->getSize() > 0);
> if (req->getVaddr() + req->getSize() - 1 < req->getVaddr())
> return make_shared<GenericPageTableFault>(req->getVaddr());
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< Process * p = tc->getProcessPtr();
---
> Process * p = tc->getProcessPtr();
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< Fault fault = p->pTable->translate(req);
< if (fault != NoFault)
< return fault;
---
> Fault fault = p->pTable->translate(req);
> if (fault != NoFault)
> return fault;
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< return NoFault;
---
> return NoFault;
> }