tlb.cc (12749:223c83ed9979) | tlb.cc (12808:f275fd1244ce) |
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1/* 2 * Copyright (c) 2001-2005 The Regents of The University of Michigan 3 * Copyright (c) 2007 MIPS Technologies, Inc. 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions are 8 * met: redistributions of source code must retain the above copyright --- 27 unchanged lines hidden (view full) --- 36#include "arch/riscv/tlb.hh" 37 38#include <string> 39#include <vector> 40 41#include "arch/riscv/faults.hh" 42#include "arch/riscv/pagetable.hh" 43#include "arch/riscv/pra_constants.hh" | 1/* 2 * Copyright (c) 2001-2005 The Regents of The University of Michigan 3 * Copyright (c) 2007 MIPS Technologies, Inc. 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions are 8 * met: redistributions of source code must retain the above copyright --- 27 unchanged lines hidden (view full) --- 36#include "arch/riscv/tlb.hh" 37 38#include <string> 39#include <vector> 40 41#include "arch/riscv/faults.hh" 42#include "arch/riscv/pagetable.hh" 43#include "arch/riscv/pra_constants.hh" |
44#include "arch/riscv/system.hh" |
|
44#include "arch/riscv/utility.hh" 45#include "base/inifile.hh" 46#include "base/str.hh" 47#include "base/trace.hh" 48#include "cpu/thread_context.hh" 49#include "debug/RiscvTLB.hh" 50#include "debug/TLB.hh" 51#include "mem/page_table.hh" --- 228 unchanged lines hidden (view full) --- 280 hits = read_hits + write_hits; 281 misses = read_misses + write_misses; 282 accesses = read_accesses + write_accesses; 283} 284 285Fault 286TLB::translateInst(const RequestPtr &req, ThreadContext *tc) 287{ | 45#include "arch/riscv/utility.hh" 46#include "base/inifile.hh" 47#include "base/str.hh" 48#include "base/trace.hh" 49#include "cpu/thread_context.hh" 50#include "debug/RiscvTLB.hh" 51#include "debug/TLB.hh" 52#include "mem/page_table.hh" --- 228 unchanged lines hidden (view full) --- 281 hits = read_hits + write_hits; 282 misses = read_misses + write_misses; 283 accesses = read_accesses + write_accesses; 284} 285 286Fault 287TLB::translateInst(const RequestPtr &req, ThreadContext *tc) 288{ |
288 if (FullSystem) 289 panic("translateInst not implemented in RISC-V.\n"); | 289 if (FullSystem) { 290 /** 291 * check if we simulate a bare metal system 292 * if so, we have no tlb, phys addr == virt addr 293 */ 294 if (static_cast<RiscvSystem *>(tc->getSystemPtr())->isBareMetal()) 295 req->setFlags(Request::PHYSICAL); |
290 | 296 |
291 Process * p = tc->getProcessPtr(); | 297 if (req->getFlags() & Request::PHYSICAL) { 298 /** 299 * we simply set the virtual address to physical address 300 */ 301 req->setPaddr(req->getVaddr()); 302 return checkCacheability(req); 303 } else { 304 /** 305 * as we currently support bare metal only, we throw a panic, 306 * if it is not a bare metal system 307 */ 308 panic("translateInst not implemented in RISC-V.\n"); 309 } 310 } else { 311 Process * p = tc->getProcessPtr(); |
292 | 312 |
293 Fault fault = p->pTable->translate(req); 294 if (fault != NoFault) 295 return fault; | 313 Fault fault = p->pTable->translate(req); 314 if (fault != NoFault) 315 return fault; |
296 | 316 |
297 return NoFault; | 317 return NoFault; 318 } |
298} 299 300Fault 301TLB::translateData(const RequestPtr &req, ThreadContext *tc, bool write) 302{ | 319} 320 321Fault 322TLB::translateData(const RequestPtr &req, ThreadContext *tc, bool write) 323{ |
303 if (FullSystem) 304 panic("translateData not implemented in RISC-V.\n"); | 324 if (FullSystem) { 325 /** 326 * check if we simulate a bare metal system 327 * if so, we have no tlb, phys addr == virt addr 328 */ 329 if (static_cast<RiscvSystem *>(tc->getSystemPtr())->isBareMetal()) 330 req->setFlags(Request::PHYSICAL); |
305 | 331 |
306 // In the O3 CPU model, sometimes a memory access will be speculatively 307 // executed along a branch that will end up not being taken where the 308 // address is invalid. In that case, return a fault rather than trying 309 // to translate it (which will cause a panic). Since RISC-V allows 310 // unaligned memory accesses, this should only happen if the request's 311 // length is long enough to wrap around from the end of the memory to the 312 // start. 313 assert(req->getSize() > 0); 314 if (req->getVaddr() + req->getSize() - 1 < req->getVaddr()) 315 return make_shared<GenericPageTableFault>(req->getVaddr()); | 332 if (req->getFlags() & Request::PHYSICAL) { 333 /** 334 * we simply set the virtual address to physical address 335 */ 336 req->setPaddr(req->getVaddr()); 337 return checkCacheability(req); 338 } else { 339 /** 340 * as we currently support bare metal only, we throw a panic, 341 * if it is not a bare metal system 342 */ 343 panic("translateData not implemented in RISC-V.\n"); 344 } 345 } else { 346 // In the O3 CPU model, sometimes a memory access will be speculatively 347 // executed along a branch that will end up not being taken where the 348 // address is invalid. In that case, return a fault rather than trying 349 // to translate it (which will cause a panic). Since RISC-V allows 350 // unaligned memory accesses, this should only happen if the request's 351 // length is long enough to wrap around from the end of the memory to 352 // the start. 353 assert(req->getSize() > 0); 354 if (req->getVaddr() + req->getSize() - 1 < req->getVaddr()) 355 return make_shared<GenericPageTableFault>(req->getVaddr()); |
316 | 356 |
317 Process * p = tc->getProcessPtr(); | 357 Process * p = tc->getProcessPtr(); |
318 | 358 |
319 Fault fault = p->pTable->translate(req); 320 if (fault != NoFault) 321 return fault; | 359 Fault fault = p->pTable->translate(req); 360 if (fault != NoFault) 361 return fault; |
322 | 362 |
323 return NoFault; | 363 return NoFault; 364 } |
324} 325 326Fault 327TLB::translateAtomic(const RequestPtr &req, ThreadContext *tc, Mode mode) 328{ 329 if (mode == Execute) 330 return translateInst(req, tc); 331 else --- 35 unchanged lines hidden --- | 365} 366 367Fault 368TLB::translateAtomic(const RequestPtr &req, ThreadContext *tc, Mode mode) 369{ 370 if (mode == Execute) 371 return translateInst(req, tc); 372 else --- 35 unchanged lines hidden --- |