1/*
2 * Copyright (c) 2001-2005 The Regents of The University of Michigan
3 * Copyright (c) 2007 MIPS Technologies, Inc.
4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are
8 * met: redistributions of source code must retain the above copyright

--- 27 unchanged lines hidden (view full) ---

36#include "arch/riscv/tlb.hh"
37
38#include <string>
39#include <vector>
40
41#include "arch/riscv/faults.hh"
42#include "arch/riscv/pagetable.hh"
43#include "arch/riscv/pra_constants.hh"
44#include "arch/riscv/utility.hh"
45#include "base/inifile.hh"
46#include "base/str.hh"
47#include "base/trace.hh"
48#include "cpu/thread_context.hh"
49#include "debug/RiscvTLB.hh"
50#include "debug/TLB.hh"
51#include "mem/page_table.hh"

--- 228 unchanged lines hidden (view full) ---

280 hits = read_hits + write_hits;
281 misses = read_misses + write_misses;
282 accesses = read_accesses + write_accesses;
283}
284
285Fault
286TLB::translateInst(const RequestPtr &req, ThreadContext *tc)
287{
288 if (FullSystem)
289 panic("translateInst not implemented in RISC-V.\n");
290
291 Process * p = tc->getProcessPtr();
292
293 Fault fault = p->pTable->translate(req);
294 if (fault != NoFault)
295 return fault;
296
297 return NoFault;
298}
299
300Fault
301TLB::translateData(const RequestPtr &req, ThreadContext *tc, bool write)
302{
303 if (FullSystem)
304 panic("translateData not implemented in RISC-V.\n");
305
306 // In the O3 CPU model, sometimes a memory access will be speculatively
307 // executed along a branch that will end up not being taken where the
308 // address is invalid. In that case, return a fault rather than trying
309 // to translate it (which will cause a panic). Since RISC-V allows
310 // unaligned memory accesses, this should only happen if the request's
311 // length is long enough to wrap around from the end of the memory to the
312 // start.
313 assert(req->getSize() > 0);
314 if (req->getVaddr() + req->getSize() - 1 < req->getVaddr())
315 return make_shared<GenericPageTableFault>(req->getVaddr());
316
317 Process * p = tc->getProcessPtr();
318
319 Fault fault = p->pTable->translate(req);
320 if (fault != NoFault)
321 return fault;
322
323 return NoFault;
324}
325
326Fault
327TLB::translateAtomic(const RequestPtr &req, ThreadContext *tc, Mode mode)
328{
329 if (mode == Execute)
330 return translateInst(req, tc);
331 else

--- 35 unchanged lines hidden ---