1/*
2 * Copyright (c) 2017 The University of Virginia
3 * Copyright 2015 LabWare
4 * Copyright 2014 Google, Inc.
5 * Copyright (c) 2007 The Regents of The University of Michigan
6 * All rights reserved.
7 *
8 * Redistribution and use in source and binary forms, with or without

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45class ThreadContext;
46
47namespace RiscvISA
48{
49
50class RemoteGDB : public BaseRemoteGDB
51{
52 protected:
53 static const int ExplicitCSRs = 4;
54
55 bool acc(Addr addr, size_t len);
56
57 class RiscvGdbRegCache : public BaseGdbRegCache
58 {
59 using BaseGdbRegCache::BaseGdbRegCache;
60 private:
61 struct {
62 uint64_t gpr[NumIntArchRegs];
63 uint64_t pc;
64 uint64_t fpr[NumFloatRegs];
65
66 uint64_t csr_base;
67 uint32_t fflags;
68 uint32_t frm;
69 uint32_t fcsr;
70 uint64_t csr[NumMiscRegs - ExplicitCSRs];
71 } __attribute__((__packed__)) r;
72 public:
73 char *data() const { return (char *)&r; }
74 size_t size() const { return sizeof(r); }
75 void getRegs(ThreadContext*);
76 void setRegs(ThreadContext*) const;
77
78 const std::string
79 name() const

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