registers.hh (13622:ba31c2a23eca) registers.hh (14177:a2aa2a947f8e)
1/*
2 * Copyright (c) 2013 ARM Limited
3 * Copyright (c) 2014-2015 Sven Karlsson
1/*
2 * Copyright (c) 2013 ARM Limited
3 * Copyright (c) 2014-2015 Sven Karlsson
4 * Copyright (c) 2019 Yifei Liu
4 * All rights reserved
5 *
6 * The license below extends only to copyright in the software and shall
7 * not be construed as granting a license to any other intellectual
8 * property including but not limited to intellectual property relating
9 * to a hardware implementation of the functionality of the software
10 * licensed hereunder. You may use the software subject to the license
11 * terms below provided that you ensure that this notice is replicated

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37 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
38 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
39 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
40 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
41 *
42 * Authors: Andreas Hansson
43 * Sven Karlsson
44 * Alec Roelke
5 * All rights reserved
6 *
7 * The license below extends only to copyright in the software and shall
8 * not be construed as granting a license to any other intellectual
9 * property including but not limited to intellectual property relating
10 * to a hardware implementation of the functionality of the software
11 * licensed hereunder. You may use the software subject to the license
12 * terms below provided that you ensure that this notice is replicated

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38 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
39 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
40 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
41 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
42 *
43 * Authors: Andreas Hansson
44 * Sven Karlsson
45 * Alec Roelke
46 * Yifei Liu
47 * Lin Cheng
48 * Xihao Chen
49 * Cheng Tan
45 */
46
47#ifndef __ARCH_RISCV_REGISTERS_HH__
48#define __ARCH_RISCV_REGISTERS_HH__
49
50#include <map>
51#include <string>
52#include <vector>

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304 CSR_HPMCOUNTER31 = 0xC1F,
305 // HPMCOUNTERH rv32 only
306
307 CSR_SSTATUS = 0x100,
308 CSR_SEDELEG = 0x102,
309 CSR_SIDELEG = 0x103,
310 CSR_SIE = 0x104,
311 CSR_STVEC = 0x105,
50 */
51
52#ifndef __ARCH_RISCV_REGISTERS_HH__
53#define __ARCH_RISCV_REGISTERS_HH__
54
55#include <map>
56#include <string>
57#include <vector>

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309 CSR_HPMCOUNTER31 = 0xC1F,
310 // HPMCOUNTERH rv32 only
311
312 CSR_SSTATUS = 0x100,
313 CSR_SEDELEG = 0x102,
314 CSR_SIDELEG = 0x103,
315 CSR_SIE = 0x104,
316 CSR_STVEC = 0x105,
317 CSR_SCOUNTEREN = 0x106,
312 CSR_SSCRATCH = 0x140,
313 CSR_SEPC = 0x141,
314 CSR_SCAUSE = 0x142,
315 CSR_STVAL = 0x143,
316 CSR_SIP = 0x144,
317 CSR_SATP = 0x180,
318
319 CSR_MVENDORID = 0xF11,
320 CSR_MARCHID = 0xF12,
321 CSR_MIMPID = 0xF13,
322 CSR_MHARTID = 0xF14,
323 CSR_MSTATUS = 0x300,
324 CSR_MISA = 0x301,
325 CSR_MEDELEG = 0x302,
326 CSR_MIDELEG = 0x303,
327 CSR_MIE = 0x304,
328 CSR_MTVEC = 0x305,
318 CSR_SSCRATCH = 0x140,
319 CSR_SEPC = 0x141,
320 CSR_SCAUSE = 0x142,
321 CSR_STVAL = 0x143,
322 CSR_SIP = 0x144,
323 CSR_SATP = 0x180,
324
325 CSR_MVENDORID = 0xF11,
326 CSR_MARCHID = 0xF12,
327 CSR_MIMPID = 0xF13,
328 CSR_MHARTID = 0xF14,
329 CSR_MSTATUS = 0x300,
330 CSR_MISA = 0x301,
331 CSR_MEDELEG = 0x302,
332 CSR_MIDELEG = 0x303,
333 CSR_MIE = 0x304,
334 CSR_MTVEC = 0x305,
335 CSR_MCOUNTEREN = 0x306,
329 CSR_MSCRATCH = 0x340,
330 CSR_MEPC = 0x341,
331 CSR_MCAUSE = 0x342,
332 CSR_MTVAL = 0x343,
333 CSR_MIP = 0x344,
334 CSR_PMPCFG0 = 0x3A0,
335 // pmpcfg1 rv32 only
336 CSR_PMPCFG2 = 0x3A2,

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473 {CSR_HPMCOUNTER30, {"hpmcounter30", MISCREG_HPMCOUNTER30}},
474 {CSR_HPMCOUNTER31, {"hpmcounter31", MISCREG_HPMCOUNTER31}},
475
476 {CSR_SSTATUS, {"sstatus", MISCREG_STATUS}},
477 {CSR_SEDELEG, {"sedeleg", MISCREG_SEDELEG}},
478 {CSR_SIDELEG, {"sideleg", MISCREG_SIDELEG}},
479 {CSR_SIE, {"sie", MISCREG_IE}},
480 {CSR_STVEC, {"stvec", MISCREG_STVEC}},
336 CSR_MSCRATCH = 0x340,
337 CSR_MEPC = 0x341,
338 CSR_MCAUSE = 0x342,
339 CSR_MTVAL = 0x343,
340 CSR_MIP = 0x344,
341 CSR_PMPCFG0 = 0x3A0,
342 // pmpcfg1 rv32 only
343 CSR_PMPCFG2 = 0x3A2,

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480 {CSR_HPMCOUNTER30, {"hpmcounter30", MISCREG_HPMCOUNTER30}},
481 {CSR_HPMCOUNTER31, {"hpmcounter31", MISCREG_HPMCOUNTER31}},
482
483 {CSR_SSTATUS, {"sstatus", MISCREG_STATUS}},
484 {CSR_SEDELEG, {"sedeleg", MISCREG_SEDELEG}},
485 {CSR_SIDELEG, {"sideleg", MISCREG_SIDELEG}},
486 {CSR_SIE, {"sie", MISCREG_IE}},
487 {CSR_STVEC, {"stvec", MISCREG_STVEC}},
488 {CSR_SCOUNTEREN, {"scounteren", MISCREG_SCOUNTEREN}},
481 {CSR_SSCRATCH, {"sscratch", MISCREG_SSCRATCH}},
482 {CSR_SEPC, {"sepc", MISCREG_SEPC}},
483 {CSR_SCAUSE, {"scause", MISCREG_SCAUSE}},
484 {CSR_STVAL, {"stval", MISCREG_STVAL}},
485 {CSR_SIP, {"sip", MISCREG_IP}},
486 {CSR_SATP, {"satp", MISCREG_SATP}},
487
488 {CSR_MVENDORID, {"mvendorid", MISCREG_VENDORID}},
489 {CSR_MARCHID, {"marchid", MISCREG_ARCHID}},
490 {CSR_MIMPID, {"mimpid", MISCREG_IMPID}},
491 {CSR_MHARTID, {"mhartid", MISCREG_HARTID}},
492 {CSR_MSTATUS, {"mstatus", MISCREG_STATUS}},
493 {CSR_MISA, {"misa", MISCREG_ISA}},
494 {CSR_MEDELEG, {"medeleg", MISCREG_MEDELEG}},
495 {CSR_MIDELEG, {"mideleg", MISCREG_MIDELEG}},
496 {CSR_MIE, {"mie", MISCREG_IE}},
497 {CSR_MTVEC, {"mtvec", MISCREG_MTVEC}},
489 {CSR_SSCRATCH, {"sscratch", MISCREG_SSCRATCH}},
490 {CSR_SEPC, {"sepc", MISCREG_SEPC}},
491 {CSR_SCAUSE, {"scause", MISCREG_SCAUSE}},
492 {CSR_STVAL, {"stval", MISCREG_STVAL}},
493 {CSR_SIP, {"sip", MISCREG_IP}},
494 {CSR_SATP, {"satp", MISCREG_SATP}},
495
496 {CSR_MVENDORID, {"mvendorid", MISCREG_VENDORID}},
497 {CSR_MARCHID, {"marchid", MISCREG_ARCHID}},
498 {CSR_MIMPID, {"mimpid", MISCREG_IMPID}},
499 {CSR_MHARTID, {"mhartid", MISCREG_HARTID}},
500 {CSR_MSTATUS, {"mstatus", MISCREG_STATUS}},
501 {CSR_MISA, {"misa", MISCREG_ISA}},
502 {CSR_MEDELEG, {"medeleg", MISCREG_MEDELEG}},
503 {CSR_MIDELEG, {"mideleg", MISCREG_MIDELEG}},
504 {CSR_MIE, {"mie", MISCREG_IE}},
505 {CSR_MTVEC, {"mtvec", MISCREG_MTVEC}},
506 {CSR_MCOUNTEREN, {"mcounteren", MISCREG_MCOUNTEREN}},
498 {CSR_MSCRATCH, {"mscratch", MISCREG_MSCRATCH}},
499 {CSR_MEPC, {"mepc", MISCREG_MEPC}},
500 {CSR_MCAUSE, {"mcause", MISCREG_MCAUSE}},
501 {CSR_MTVAL, {"mtval", MISCREG_MTVAL}},
502 {CSR_MIP, {"mip", MISCREG_IP}},
503 {CSR_PMPCFG0, {"pmpcfg0", MISCREG_PMPCFG0}},
504 // pmpcfg1 rv32 only
505 {CSR_PMPCFG2, {"pmpcfg2", MISCREG_PMPCFG2}},

--- 222 unchanged lines hidden --- 		507 {CSR_MSCRATCH, {"mscratch", MISCREG_MSCRATCH}},
508 {CSR_MEPC, {"mepc", MISCREG_MEPC}},
509 {CSR_MCAUSE, {"mcause", MISCREG_MCAUSE}},
510 {CSR_MTVAL, {"mtval", MISCREG_MTVAL}},
511 {CSR_MIP, {"mip", MISCREG_IP}},
512 {CSR_PMPCFG0, {"pmpcfg0", MISCREG_PMPCFG0}},
513 // pmpcfg1 rv32 only
514 {CSR_PMPCFG2, {"pmpcfg2", MISCREG_PMPCFG2}},

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