registers.hh (13611:c8b7847b4171) registers.hh (13612:12ae022f3a30)
1/*
2 * Copyright (c) 2013 ARM Limited
3 * Copyright (c) 2014-2015 Sven Karlsson
4 * All rights reserved
5 *
6 * The license below extends only to copyright in the software and shall
7 * not be construed as granting a license to any other intellectual
8 * property including but not limited to intellectual property relating

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59#include "base/types.hh"
60
61namespace RiscvISA {
62
63using RiscvISAInst::MaxInstSrcRegs;
64using RiscvISAInst::MaxInstDestRegs;
65const int MaxMiscDestRegs = 1;
66
1/*
2 * Copyright (c) 2013 ARM Limited
3 * Copyright (c) 2014-2015 Sven Karlsson
4 * All rights reserved
5 *
6 * The license below extends only to copyright in the software and shall
7 * not be construed as granting a license to any other intellectual
8 * property including but not limited to intellectual property relating

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59#include "base/types.hh"
60
61namespace RiscvISA {
62
63using RiscvISAInst::MaxInstSrcRegs;
64using RiscvISAInst::MaxInstDestRegs;
65const int MaxMiscDestRegs = 1;
66
67typedef RegVal IntReg;
68typedef RegVal FloatReg;
69typedef uint8_t CCReg; // Not applicable to Riscv
67typedef uint8_t CCReg; // Not applicable to Riscv
70typedef RegVal MiscReg;
71
72// Not applicable to RISC-V
73using VecElem = ::DummyVecElem;
74using VecReg = ::DummyVecReg;
75using ConstVecReg = ::DummyConstVecReg;
76using VecRegContainer = ::DummyVecRegContainer;
77constexpr unsigned NumVecElemPerVecReg = ::DummyNumVecElemPerVecReg;
78constexpr size_t VecRegSizeBytes = ::DummyVecRegSizeBytes;

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637 Bitfield<7> mti;
638 Bitfield<5> sti;
639 Bitfield<4> uti;
640 Bitfield<3> msi;
641 Bitfield<1> ssi;
642 Bitfield<0> usi;
643EndBitUnion(INTERRUPT)
644
68
69// Not applicable to RISC-V
70using VecElem = ::DummyVecElem;
71using VecReg = ::DummyVecReg;
72using ConstVecReg = ::DummyConstVecReg;
73using VecRegContainer = ::DummyVecRegContainer;
74constexpr unsigned NumVecElemPerVecReg = ::DummyNumVecElemPerVecReg;
75constexpr size_t VecRegSizeBytes = ::DummyVecRegSizeBytes;

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634 Bitfield<7> mti;
635 Bitfield<5> sti;
636 Bitfield<4> uti;
637 Bitfield<3> msi;
638 Bitfield<1> ssi;
639 Bitfield<0> usi;
640EndBitUnion(INTERRUPT)
641
645const off_t MXL_OFFSET = (sizeof(MiscReg) * 8 - 2);
642const off_t MXL_OFFSET = (sizeof(uint64_t) * 8 - 2);
646const off_t SXL_OFFSET = 34;
647const off_t UXL_OFFSET = 32;
648const off_t FS_OFFSET = 13;
649const off_t FRM_OFFSET = 5;
650
643const off_t SXL_OFFSET = 34;
644const off_t UXL_OFFSET = 32;
645const off_t FS_OFFSET = 13;
646const off_t FRM_OFFSET = 5;
647
651const MiscReg ISA_MXL_MASK = 3ULL << MXL_OFFSET;
652const MiscReg ISA_EXT_MASK = mask(26);
653const MiscReg MISA_MASK = ISA_MXL_MASK | ISA_EXT_MASK;
648const RegVal ISA_MXL_MASK = 3ULL << MXL_OFFSET;
649const RegVal ISA_EXT_MASK = mask(26);
650const RegVal MISA_MASK = ISA_MXL_MASK | ISA_EXT_MASK;
654
651
655const MiscReg STATUS_SD_MASK = 1ULL << ((sizeof(MiscReg) * 8) - 1);
656const MiscReg STATUS_SXL_MASK = 3ULL << SXL_OFFSET;
657const MiscReg STATUS_UXL_MASK = 3ULL << UXL_OFFSET;
658const MiscReg STATUS_TSR_MASK = 1ULL << 22;
659const MiscReg STATUS_TW_MASK = 1ULL << 21;
660const MiscReg STATUS_TVM_MASK = 1ULL << 20;
661const MiscReg STATUS_MXR_MASK = 1ULL << 19;
662const MiscReg STATUS_SUM_MASK = 1ULL << 18;
663const MiscReg STATUS_MPRV_MASK = 1ULL << 17;
664const MiscReg STATUS_XS_MASK = 3ULL << 15;
665const MiscReg STATUS_FS_MASK = 3ULL << FS_OFFSET;
666const MiscReg STATUS_MPP_MASK = 3ULL << 11;
667const MiscReg STATUS_SPP_MASK = 1ULL << 8;
668const MiscReg STATUS_MPIE_MASK = 1ULL << 7;
669const MiscReg STATUS_SPIE_MASK = 1ULL << 5;
670const MiscReg STATUS_UPIE_MASK = 1ULL << 4;
671const MiscReg STATUS_MIE_MASK = 1ULL << 3;
672const MiscReg STATUS_SIE_MASK = 1ULL << 1;
673const MiscReg STATUS_UIE_MASK = 1ULL << 0;
674const MiscReg MSTATUS_MASK = STATUS_SD_MASK | STATUS_SXL_MASK |
675 STATUS_UXL_MASK | STATUS_TSR_MASK |
676 STATUS_TW_MASK | STATUS_TVM_MASK |
677 STATUS_MXR_MASK | STATUS_SUM_MASK |
678 STATUS_MPRV_MASK | STATUS_XS_MASK |
679 STATUS_FS_MASK | STATUS_MPP_MASK |
680 STATUS_SPP_MASK | STATUS_MPIE_MASK |
681 STATUS_SPIE_MASK | STATUS_UPIE_MASK |
682 STATUS_MIE_MASK | STATUS_SIE_MASK |
683 STATUS_UIE_MASK;
684const MiscReg SSTATUS_MASK = STATUS_SD_MASK | STATUS_UXL_MASK |
685 STATUS_MXR_MASK | STATUS_SUM_MASK |
686 STATUS_XS_MASK | STATUS_FS_MASK |
687 STATUS_SPP_MASK | STATUS_SPIE_MASK |
688 STATUS_UPIE_MASK | STATUS_SIE_MASK |
689 STATUS_UIE_MASK;
690const MiscReg USTATUS_MASK = STATUS_SD_MASK | STATUS_MXR_MASK |
691 STATUS_SUM_MASK | STATUS_XS_MASK |
692 STATUS_FS_MASK | STATUS_UPIE_MASK |
693 STATUS_UIE_MASK;
652const RegVal STATUS_SD_MASK = 1ULL << ((sizeof(uint64_t) * 8) - 1);
653const RegVal STATUS_SXL_MASK = 3ULL << SXL_OFFSET;
654const RegVal STATUS_UXL_MASK = 3ULL << UXL_OFFSET;
655const RegVal STATUS_TSR_MASK = 1ULL << 22;
656const RegVal STATUS_TW_MASK = 1ULL << 21;
657const RegVal STATUS_TVM_MASK = 1ULL << 20;
658const RegVal STATUS_MXR_MASK = 1ULL << 19;
659const RegVal STATUS_SUM_MASK = 1ULL << 18;
660const RegVal STATUS_MPRV_MASK = 1ULL << 17;
661const RegVal STATUS_XS_MASK = 3ULL << 15;
662const RegVal STATUS_FS_MASK = 3ULL << FS_OFFSET;
663const RegVal STATUS_MPP_MASK = 3ULL << 11;
664const RegVal STATUS_SPP_MASK = 1ULL << 8;
665const RegVal STATUS_MPIE_MASK = 1ULL << 7;
666const RegVal STATUS_SPIE_MASK = 1ULL << 5;
667const RegVal STATUS_UPIE_MASK = 1ULL << 4;
668const RegVal STATUS_MIE_MASK = 1ULL << 3;
669const RegVal STATUS_SIE_MASK = 1ULL << 1;
670const RegVal STATUS_UIE_MASK = 1ULL << 0;
671const RegVal MSTATUS_MASK = STATUS_SD_MASK | STATUS_SXL_MASK |
672 STATUS_UXL_MASK | STATUS_TSR_MASK |
673 STATUS_TW_MASK | STATUS_TVM_MASK |
674 STATUS_MXR_MASK | STATUS_SUM_MASK |
675 STATUS_MPRV_MASK | STATUS_XS_MASK |
676 STATUS_FS_MASK | STATUS_MPP_MASK |
677 STATUS_SPP_MASK | STATUS_MPIE_MASK |
678 STATUS_SPIE_MASK | STATUS_UPIE_MASK |
679 STATUS_MIE_MASK | STATUS_SIE_MASK |
680 STATUS_UIE_MASK;
681const RegVal SSTATUS_MASK = STATUS_SD_MASK | STATUS_UXL_MASK |
682 STATUS_MXR_MASK | STATUS_SUM_MASK |
683 STATUS_XS_MASK | STATUS_FS_MASK |
684 STATUS_SPP_MASK | STATUS_SPIE_MASK |
685 STATUS_UPIE_MASK | STATUS_SIE_MASK |
686 STATUS_UIE_MASK;
687const RegVal USTATUS_MASK = STATUS_SD_MASK | STATUS_MXR_MASK |
688 STATUS_SUM_MASK | STATUS_XS_MASK |
689 STATUS_FS_MASK | STATUS_UPIE_MASK |
690 STATUS_UIE_MASK;
694
691
695const MiscReg MEI_MASK = 1ULL << 11;
696const MiscReg SEI_MASK = 1ULL << 9;
697const MiscReg UEI_MASK = 1ULL << 8;
698const MiscReg MTI_MASK = 1ULL << 7;
699const MiscReg STI_MASK = 1ULL << 5;
700const MiscReg UTI_MASK = 1ULL << 4;
701const MiscReg MSI_MASK = 1ULL << 3;
702const MiscReg SSI_MASK = 1ULL << 1;
703const MiscReg USI_MASK = 1ULL << 0;
704const MiscReg MI_MASK = MEI_MASK | SEI_MASK | UEI_MASK |
705 MTI_MASK | STI_MASK | UTI_MASK |
706 MSI_MASK | SSI_MASK | USI_MASK;
707const MiscReg SI_MASK = SEI_MASK | UEI_MASK |
708 STI_MASK | UTI_MASK |
709 SSI_MASK | USI_MASK;
710const MiscReg UI_MASK = UEI_MASK | UTI_MASK | USI_MASK;
711const MiscReg FFLAGS_MASK = (1 << FRM_OFFSET) - 1;
712const MiscReg FRM_MASK = 0x7;
692const RegVal MEI_MASK = 1ULL << 11;
693const RegVal SEI_MASK = 1ULL << 9;
694const RegVal UEI_MASK = 1ULL << 8;
695const RegVal MTI_MASK = 1ULL << 7;
696const RegVal STI_MASK = 1ULL << 5;
697const RegVal UTI_MASK = 1ULL << 4;
698const RegVal MSI_MASK = 1ULL << 3;
699const RegVal SSI_MASK = 1ULL << 1;
700const RegVal USI_MASK = 1ULL << 0;
701const RegVal MI_MASK = MEI_MASK | SEI_MASK | UEI_MASK |
702 MTI_MASK | STI_MASK | UTI_MASK |
703 MSI_MASK | SSI_MASK | USI_MASK;
704const RegVal SI_MASK = SEI_MASK | UEI_MASK |
705 STI_MASK | UTI_MASK |
706 SSI_MASK | USI_MASK;
707const RegVal UI_MASK = UEI_MASK | UTI_MASK | USI_MASK;
708const RegVal FFLAGS_MASK = (1 << FRM_OFFSET) - 1;
709const RegVal FRM_MASK = 0x7;
713
710
714const std::map<int, MiscReg> CSRMasks = {
711const std::map<int, RegVal> CSRMasks = {
715 {CSR_USTATUS, USTATUS_MASK},
716 {CSR_UIE, UI_MASK},
717 {CSR_UIP, UI_MASK},
718 {CSR_FFLAGS, FFLAGS_MASK},
719 {CSR_FRM, FRM_MASK},
720 {CSR_FCSR, FFLAGS_MASK | (FRM_MASK << FRM_OFFSET)},
721 {CSR_SSTATUS, SSTATUS_MASK},
722 {CSR_SIE, SI_MASK},
723 {CSR_SIP, SI_MASK},
724 {CSR_MSTATUS, MSTATUS_MASK},
725 {CSR_MISA, MISA_MASK},
726 {CSR_MIE, MI_MASK},
727 {CSR_MIP, MI_MASK}
728};
729
730}
731
732#endif // __ARCH_RISCV_REGISTERS_HH__
712 {CSR_USTATUS, USTATUS_MASK},
713 {CSR_UIE, UI_MASK},
714 {CSR_UIP, UI_MASK},
715 {CSR_FFLAGS, FFLAGS_MASK},
716 {CSR_FRM, FRM_MASK},
717 {CSR_FCSR, FFLAGS_MASK | (FRM_MASK << FRM_OFFSET)},
718 {CSR_SSTATUS, SSTATUS_MASK},
719 {CSR_SIE, SI_MASK},
720 {CSR_SIP, SI_MASK},
721 {CSR_MSTATUS, MSTATUS_MASK},
722 {CSR_MISA, MISA_MASK},
723 {CSR_MIE, MI_MASK},
724 {CSR_MIP, MI_MASK}
725};
726
727}
728
729#endif // __ARCH_RISCV_REGISTERS_HH__