registers.hh (13610:5d5404ac6288) | registers.hh (13611:c8b7847b4171) |
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1/* 2 * Copyright (c) 2013 ARM Limited 3 * Copyright (c) 2014-2015 Sven Karlsson 4 * All rights reserved 5 * 6 * The license below extends only to copyright in the software and shall 7 * not be construed as granting a license to any other intellectual 8 * property including but not limited to intellectual property relating --- 51 unchanged lines hidden (view full) --- 60 61namespace RiscvISA { 62 63using RiscvISAInst::MaxInstSrcRegs; 64using RiscvISAInst::MaxInstDestRegs; 65const int MaxMiscDestRegs = 1; 66 67typedef RegVal IntReg; | 1/* 2 * Copyright (c) 2013 ARM Limited 3 * Copyright (c) 2014-2015 Sven Karlsson 4 * All rights reserved 5 * 6 * The license below extends only to copyright in the software and shall 7 * not be construed as granting a license to any other intellectual 8 * property including but not limited to intellectual property relating --- 51 unchanged lines hidden (view full) --- 60 61namespace RiscvISA { 62 63using RiscvISAInst::MaxInstSrcRegs; 64using RiscvISAInst::MaxInstDestRegs; 65const int MaxMiscDestRegs = 1; 66 67typedef RegVal IntReg; |
68typedef RegVal FloatRegBits; | 68typedef RegVal FloatReg; |
69typedef uint8_t CCReg; // Not applicable to Riscv 70typedef RegVal MiscReg; 71 72// Not applicable to RISC-V 73using VecElem = ::DummyVecElem; 74using VecReg = ::DummyVecReg; 75using ConstVecReg = ::DummyConstVecReg; 76using VecRegContainer = ::DummyVecRegContainer; --- 656 unchanged lines hidden --- | 69typedef uint8_t CCReg; // Not applicable to Riscv 70typedef RegVal MiscReg; 71 72// Not applicable to RISC-V 73using VecElem = ::DummyVecElem; 74using VecReg = ::DummyVecReg; 75using ConstVecReg = ::DummyConstVecReg; 76using VecRegContainer = ::DummyVecRegContainer; --- 656 unchanged lines hidden --- |