registers.hh (13592:b8972ccebd63) registers.hh (13610:5d5404ac6288)
1/*
2 * Copyright (c) 2013 ARM Limited
3 * Copyright (c) 2014-2015 Sven Karlsson
4 * All rights reserved
5 *
6 * The license below extends only to copyright in the software and shall
7 * not be construed as granting a license to any other intellectual
8 * property including but not limited to intellectual property relating

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47#ifndef __ARCH_RISCV_REGISTERS_HH__
48#define __ARCH_RISCV_REGISTERS_HH__
49
50#include <map>
51#include <string>
52#include <vector>
53
54#include "arch/generic/types.hh"
1/*
2 * Copyright (c) 2013 ARM Limited
3 * Copyright (c) 2014-2015 Sven Karlsson
4 * All rights reserved
5 *
6 * The license below extends only to copyright in the software and shall
7 * not be construed as granting a license to any other intellectual
8 * property including but not limited to intellectual property relating

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47#ifndef __ARCH_RISCV_REGISTERS_HH__
48#define __ARCH_RISCV_REGISTERS_HH__
49
50#include <map>
51#include <string>
52#include <vector>
53
54#include "arch/generic/types.hh"
55#include "arch/generic/vec_pred_reg.hh"
55#include "arch/generic/vec_reg.hh"
56#include "arch/isa_traits.hh"
57#include "arch/riscv/generated/max_inst_regs.hh"
58#include "base/types.hh"
59
60namespace RiscvISA {
61
62using RiscvISAInst::MaxInstSrcRegs;
63using RiscvISAInst::MaxInstDestRegs;
64const int MaxMiscDestRegs = 1;
65
66typedef RegVal IntReg;
67typedef RegVal FloatRegBits;
68typedef uint8_t CCReg; // Not applicable to Riscv
69typedef RegVal MiscReg;
70
56#include "arch/generic/vec_reg.hh"
57#include "arch/isa_traits.hh"
58#include "arch/riscv/generated/max_inst_regs.hh"
59#include "base/types.hh"
60
61namespace RiscvISA {
62
63using RiscvISAInst::MaxInstSrcRegs;
64using RiscvISAInst::MaxInstDestRegs;
65const int MaxMiscDestRegs = 1;
66
67typedef RegVal IntReg;
68typedef RegVal FloatRegBits;
69typedef uint8_t CCReg; // Not applicable to Riscv
70typedef RegVal MiscReg;
71
71// dummy typedefs since we don't have vector regs
72const unsigned NumVecElemPerVecReg = 2;
73using VecElem = uint32_t;
74using VecReg = ::VecRegT<VecElem, NumVecElemPerVecReg, false>;
75using ConstVecReg = ::VecRegT<VecElem, NumVecElemPerVecReg, true>;
76using VecRegContainer = VecReg::Container;
72// Not applicable to RISC-V
73using VecElem = ::DummyVecElem;
74using VecReg = ::DummyVecReg;
75using ConstVecReg = ::DummyConstVecReg;
76using VecRegContainer = ::DummyVecRegContainer;
77constexpr unsigned NumVecElemPerVecReg = ::DummyNumVecElemPerVecReg;
78constexpr size_t VecRegSizeBytes = ::DummyVecRegSizeBytes;
77
79
80// Not applicable to RISC-V
81using VecPredReg = ::DummyVecPredReg;
82using ConstVecPredReg = ::DummyConstVecPredReg;
83using VecPredRegContainer = ::DummyVecPredRegContainer;
84constexpr size_t VecPredRegSizeBits = ::DummyVecPredRegSizeBits;
85constexpr bool VecPredRegHasPackedRepr = ::DummyVecPredRegHasPackedRepr;
86
78const int NumIntArchRegs = 32;
79const int NumMicroIntRegs = 1;
80const int NumIntRegs = NumIntArchRegs + NumMicroIntRegs;
81const int NumFloatRegs = 32;
87const int NumIntArchRegs = 32;
88const int NumMicroIntRegs = 1;
89const int NumIntRegs = NumIntArchRegs + NumMicroIntRegs;
90const int NumFloatRegs = 32;
82// This has to be one to prevent warnings that are treated as errors
83const unsigned NumVecRegs = 1;
91
92const unsigned NumVecRegs = 1; // Not applicable to RISC-V
93 // (1 to prevent warnings)
94const int NumVecPredRegs = 1; // Not applicable to RISC-V
95 // (1 to prevent warnings)
96
84const int NumCCRegs = 0;
85
86// Semantically meaningful register indices
87const int ZeroReg = 0;
88const int ReturnAddrReg = 1;
89const int StackPointerReg = 2;
90const int GlobalPointerReg = 3;
91const int ThreadPointerReg = 4;

--- 628 unchanged lines hidden --- 		97const int NumCCRegs = 0;
98
99// Semantically meaningful register indices
100const int ZeroReg = 0;
101const int ReturnAddrReg = 1;
102const int StackPointerReg = 2;
103const int GlobalPointerReg = 3;
104const int ThreadPointerReg = 4;

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