registers.hh (12850:7036cad54910) registers.hh (13556:9f57bb56153a)
1/*
2 * Copyright (c) 2013 ARM Limited
3 * Copyright (c) 2014-2015 Sven Karlsson
4 * All rights reserved
5 *
6 * The license below extends only to copyright in the software and shall
7 * not be construed as granting a license to any other intellectual
8 * property including but not limited to intellectual property relating

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58#include "base/types.hh"
59
60namespace RiscvISA {
61
62using RiscvISAInst::MaxInstSrcRegs;
63using RiscvISAInst::MaxInstDestRegs;
64const int MaxMiscDestRegs = 1;
65
1/*
2 * Copyright (c) 2013 ARM Limited
3 * Copyright (c) 2014-2015 Sven Karlsson
4 * All rights reserved
5 *
6 * The license below extends only to copyright in the software and shall
7 * not be construed as granting a license to any other intellectual
8 * property including but not limited to intellectual property relating

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58#include "base/types.hh"
59
60namespace RiscvISA {
61
62using RiscvISAInst::MaxInstSrcRegs;
63using RiscvISAInst::MaxInstDestRegs;
64const int MaxMiscDestRegs = 1;
65
66typedef uint64_t IntReg;
67typedef uint64_t FloatRegBits;
68typedef double FloatReg;
66typedef RegVal IntReg;
67typedef RegVal FloatRegBits;
68typedef FloatRegVal FloatReg;
69typedef uint8_t CCReg; // Not applicable to Riscv
69typedef uint8_t CCReg; // Not applicable to Riscv
70typedef uint64_t MiscReg;
70typedef RegVal MiscReg;
71
72// dummy typedefs since we don't have vector regs
73const unsigned NumVecElemPerVecReg = 2;
74using VecElem = uint32_t;
75using VecReg = ::VecRegT<VecElem, NumVecElemPerVecReg, false>;
76using ConstVecReg = ::VecRegT<VecElem, NumVecElemPerVecReg, true>;
77using VecRegContainer = VecReg::Container;
78

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72// dummy typedefs since we don't have vector regs
73const unsigned NumVecElemPerVecReg = 2;
74using VecElem = uint32_t;
75using VecReg = ::VecRegT<VecElem, NumVecElemPerVecReg, false>;
76using ConstVecReg = ::VecRegT<VecElem, NumVecElemPerVecReg, true>;
77using VecRegContainer = VecReg::Container;
78

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