registers.hh (12695:3df197da6069) registers.hh (12850:7036cad54910)
1/*
2 * Copyright (c) 2013 ARM Limited
3 * Copyright (c) 2014-2015 Sven Karlsson
4 * All rights reserved
5 *
6 * The license below extends only to copyright in the software and shall
7 * not be construed as granting a license to any other intellectual
8 * property including but not limited to intellectual property relating

--- 569 unchanged lines hidden (view full) ---

578 {CSR_TDATA1, {"tdata1", MISCREG_TDATA1}},
579 {CSR_TDATA2, {"tdata2", MISCREG_TDATA2}},
580 {CSR_TDATA3, {"tdata3", MISCREG_TDATA3}},
581 {CSR_DCSR, {"dcsr", MISCREG_DCSR}},
582 {CSR_DPC, {"dpc", MISCREG_DPC}},
583 {CSR_DSCRATCH, {"dscratch", MISCREG_DSCRATCH}}
584};
585
1/*
2 * Copyright (c) 2013 ARM Limited
3 * Copyright (c) 2014-2015 Sven Karlsson
4 * All rights reserved
5 *
6 * The license below extends only to copyright in the software and shall
7 * not be construed as granting a license to any other intellectual
8 * property including but not limited to intellectual property relating

--- 569 unchanged lines hidden (view full) ---

578 {CSR_TDATA1, {"tdata1", MISCREG_TDATA1}},
579 {CSR_TDATA2, {"tdata2", MISCREG_TDATA2}},
580 {CSR_TDATA3, {"tdata3", MISCREG_TDATA3}},
581 {CSR_DCSR, {"dcsr", MISCREG_DCSR}},
582 {CSR_DPC, {"dpc", MISCREG_DPC}},
583 {CSR_DSCRATCH, {"dscratch", MISCREG_DSCRATCH}}
584};
585
586/**
587 * These fields are specified in the RISC-V Instruction Set Manual, Volume II,
588 * v1.10, accessible at www.riscv.org. in Figure 3.7. The main register that
589 * uses these fields is the MSTATUS register, which is shadowed by two others
590 * accessible at lower privilege levels (SSTATUS and USTATUS) that can't see
591 * the fields for higher privileges.
592 */
593BitUnion64(STATUS)
594 Bitfield<63> sd;
595 Bitfield<35, 34> sxl;
596 Bitfield<33, 32> uxl;
597 Bitfield<22> tsr;
598 Bitfield<21> tw;
599 Bitfield<20> tvm;
600 Bitfield<19> mxr;
601 Bitfield<18> sum;
602 Bitfield<17> mprv;
603 Bitfield<16, 15> xs;
604 Bitfield<14, 13> fs;
605 Bitfield<12, 11> mpp;
606 Bitfield<8> spp;
607 Bitfield<7> mpie;
608 Bitfield<5> spie;
609 Bitfield<4> upie;
610 Bitfield<3> mie;
611 Bitfield<1> sie;
612 Bitfield<0> uie;
613EndBitUnion(STATUS)
614
615/**
616 * These fields are specified in the RISC-V Instruction Set Manual, Volume II,
617 * v1.10 in Figures 3.11 and 3.12, accessible at www.riscv.org. Both the MIP
618 * and MIE registers have the same fields, so accesses to either should use
619 * this bit union.
620 */
621BitUnion64(INTERRUPT)
622 Bitfield<11> mei;
623 Bitfield<9> sei;
624 Bitfield<8> uei;
625 Bitfield<7> mti;
626 Bitfield<5> sti;
627 Bitfield<4> uti;
628 Bitfield<3> msi;
629 Bitfield<1> ssi;
630 Bitfield<0> usi;
631EndBitUnion(INTERRUPT)
632
586const off_t MXL_OFFSET = (sizeof(MiscReg) * 8 - 2);
587const off_t SXL_OFFSET = 34;
588const off_t UXL_OFFSET = 32;
589const off_t FS_OFFSET = 13;
590const off_t FRM_OFFSET = 5;
591
592const MiscReg ISA_MXL_MASK = 3ULL << MXL_OFFSET;
593const MiscReg ISA_EXT_MASK = mask(26);

--- 80 unchanged lines hidden --- 		633const off_t MXL_OFFSET = (sizeof(MiscReg) * 8 - 2);
634const off_t SXL_OFFSET = 34;
635const off_t UXL_OFFSET = 32;
636const off_t FS_OFFSET = 13;
637const off_t FRM_OFFSET = 5;
638
639const MiscReg ISA_MXL_MASK = 3ULL << MXL_OFFSET;
640const MiscReg ISA_EXT_MASK = mask(26);

--- 80 unchanged lines hidden ---