registers.hh (12119:e9ef3ee3171d) registers.hh (12135:44bd81faf754)
1/*
2 * Copyright (c) 2013 ARM Limited
3 * Copyright (c) 2014-2015 Sven Karlsson
4 * All rights reserved
5 *
6 * The license below extends only to copyright in the software and shall
7 * not be construed as granting a license to any other intellectual
8 * property including but not limited to intellectual property relating

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88// Semantically meaningful register indices
89const int ZeroReg = 0;
90const int ReturnAddrReg = 1;
91const int StackPointerReg = 2;
92const int GlobalPointerReg = 3;
93const int ThreadPointerReg = 4;
94const int FramePointerReg = 8;
95const std::vector<int> ReturnValueRegs = {10, 11};
1/*
2 * Copyright (c) 2013 ARM Limited
3 * Copyright (c) 2014-2015 Sven Karlsson
4 * All rights reserved
5 *
6 * The license below extends only to copyright in the software and shall
7 * not be construed as granting a license to any other intellectual
8 * property including but not limited to intellectual property relating

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88// Semantically meaningful register indices
89const int ZeroReg = 0;
90const int ReturnAddrReg = 1;
91const int StackPointerReg = 2;
92const int GlobalPointerReg = 3;
93const int ThreadPointerReg = 4;
94const int FramePointerReg = 8;
95const std::vector<int> ReturnValueRegs = {10, 11};
96const int ReturnValueReg = ReturnValueRegs[0];
96const int ReturnValueReg M5_VAR_USED = ReturnValueRegs[0];
97const std::vector<int> ArgumentRegs = {10, 11, 12, 13, 14, 15, 16, 17};
98const int AMOTempReg = 32;
99
100const std::vector<std::string> IntRegNames = {
101 "zero", "ra", "sp", "gp",
102 "tp", "t0", "t1", "t2",
103 "s0", "s1", "a0", "a1",
104 "a2", "a3", "a4", "a5",

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113 "fs0", "fs1", "fa0", "fa1",
114 "fa2", "fa3", "fa4", "fa5",
115 "fa6", "fa7", "fs2", "fs3",
116 "fs4", "fs5", "fs6", "fs7",
117 "fs8", "fs9", "fs10", "fs11",
118 "ft8", "ft9", "ft10", "ft11"
119};
120
97const std::vector<int> ArgumentRegs = {10, 11, 12, 13, 14, 15, 16, 17};
98const int AMOTempReg = 32;
99
100const std::vector<std::string> IntRegNames = {
101 "zero", "ra", "sp", "gp",
102 "tp", "t0", "t1", "t2",
103 "s0", "s1", "a0", "a1",
104 "a2", "a3", "a4", "a5",

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113 "fs0", "fs1", "fa0", "fa1",
114 "fa2", "fa3", "fa4", "fa5",
115 "fa6", "fa7", "fs2", "fs3",
116 "fs4", "fs5", "fs6", "fs7",
117 "fs8", "fs9", "fs10", "fs11",
118 "ft8", "ft9", "ft10", "ft11"
119};
120
121const int SyscallNumReg = ArgumentRegs[7];
121const int SyscallNumReg M5_VAR_USED = ArgumentRegs[7];
122const std::vector<int> SyscallArgumentRegs = {ArgumentRegs[0], ArgumentRegs[1],
123 ArgumentRegs[2], ArgumentRegs[3]};
122const std::vector<int> SyscallArgumentRegs = {ArgumentRegs[0], ArgumentRegs[1],
123 ArgumentRegs[2], ArgumentRegs[3]};
124const int SyscallPseudoReturnReg = ReturnValueRegs[0];
124const int SyscallPseudoReturnReg M5_VAR_USED = ReturnValueRegs[0];
125
126enum MiscRegIndex {
127 MISCREG_USTATUS = 0x000,
128 MISCREG_UIE = 0x004,
129 MISCREG_UTVEC = 0x005,
130 MISCREG_USCRATCH = 0x040,
131 MISCREG_UEPC = 0x041,
132 MISCREG_UCAUSE = 0x042,

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126enum MiscRegIndex {
127 MISCREG_USTATUS = 0x000,
128 MISCREG_UIE = 0x004,
129 MISCREG_UTVEC = 0x005,
130 MISCREG_USCRATCH = 0x040,
131 MISCREG_UEPC = 0x041,
132 MISCREG_UCAUSE = 0x042,

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