registers.hh (11963:3fb6bb58e6a4) registers.hh (12104:edd63f9c6184)
1/*
2 * Copyright (c) 2013 ARM Limited
3 * Copyright (c) 2014-2015 Sven Karlsson
4 * All rights reserved
5 *
6 * The license below extends only to copyright in the software and shall
7 * not be construed as granting a license to any other intellectual
8 * property including but not limited to intellectual property relating

--- 36 unchanged lines hidden (view full) ---

45 */
46
47#ifndef __ARCH_RISCV_REGISTERS_HH__
48#define __ARCH_RISCV_REGISTERS_HH__
49
50#include <map>
51#include <string>
52
1/*
2 * Copyright (c) 2013 ARM Limited
3 * Copyright (c) 2014-2015 Sven Karlsson
4 * All rights reserved
5 *
6 * The license below extends only to copyright in the software and shall
7 * not be construed as granting a license to any other intellectual
8 * property including but not limited to intellectual property relating

--- 36 unchanged lines hidden (view full) ---

45 */
46
47#ifndef __ARCH_RISCV_REGISTERS_HH__
48#define __ARCH_RISCV_REGISTERS_HH__
49
50#include <map>
51#include <string>
52
53#include "arch/generic/types.hh"
53#include "arch/isa_traits.hh"
54#include "arch/riscv/generated/max_inst_regs.hh"
55#include "base/types.hh"
56
57namespace RiscvISA {
58
59using RiscvISAInst::MaxInstSrcRegs;
60using RiscvISAInst::MaxInstDestRegs;
61const int MaxMiscDestRegs = 1;
62
54#include "arch/isa_traits.hh"
55#include "arch/riscv/generated/max_inst_regs.hh"
56#include "base/types.hh"
57
58namespace RiscvISA {
59
60using RiscvISAInst::MaxInstSrcRegs;
61using RiscvISAInst::MaxInstDestRegs;
62const int MaxMiscDestRegs = 1;
63
63typedef uint_fast16_t RegIndex;
64typedef uint64_t IntReg;
65typedef uint64_t FloatRegBits;
66typedef double FloatReg;
67typedef uint8_t CCReg; // Not applicable to Riscv
68typedef uint64_t MiscReg;
69
70const int NumIntArchRegs = 32;
71const int NumMicroIntRegs = 1;
72const int NumIntRegs = NumIntArchRegs + NumMicroIntRegs;
73const int NumFloatRegs = 32;
74const int NumCCRegs = 0;
75const int NumMiscRegs = 4096;
76
64typedef uint64_t IntReg;
65typedef uint64_t FloatRegBits;
66typedef double FloatReg;
67typedef uint8_t CCReg; // Not applicable to Riscv
68typedef uint64_t MiscReg;
69
70const int NumIntArchRegs = 32;
71const int NumMicroIntRegs = 1;
72const int NumIntRegs = NumIntArchRegs + NumMicroIntRegs;
73const int NumFloatRegs = 32;
74const int NumCCRegs = 0;
75const int NumMiscRegs = 4096;
76
77// These help enumerate all the registers for dependence tracking.
78const int FP_Reg_Base = NumIntRegs;
79const int CC_Reg_Base = FP_Reg_Base + NumFloatRegs;
80const int Misc_Reg_Base = CC_Reg_Base + NumCCRegs;
81const int Max_Reg_Index = Misc_Reg_Base + NumMiscRegs;
82
83// Semantically meaningful register indices
84const int ZeroReg = 0;
85const int ReturnAddrReg = 1;
86const int StackPointerReg = 2;
87const int GlobalPointerReg = 3;
88const int ThreadPointerReg = 4;
89const int FramePointerReg = 8;
90const int ReturnValueRegs[] = {10, 11};

--- 107 unchanged lines hidden --- 		77// Semantically meaningful register indices
78const int ZeroReg = 0;
79const int ReturnAddrReg = 1;
80const int StackPointerReg = 2;
81const int GlobalPointerReg = 3;
82const int ThreadPointerReg = 4;
83const int FramePointerReg = 8;
84const int ReturnValueRegs[] = {10, 11};

--- 107 unchanged lines hidden ---