registers.hh (11911:fecd8de0ec8e) | registers.hh (11963:3fb6bb58e6a4) |
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1/* 2 * Copyright (c) 2013 ARM Limited 3 * Copyright (c) 2014-2015 Sven Karlsson 4 * All rights reserved 5 * 6 * The license below extends only to copyright in the software and shall 7 * not be construed as granting a license to any other intellectual 8 * property including but not limited to intellectual property relating --- 92 unchanged lines hidden (view full) --- 101 "s8", "s9", "s10", "s11", 102 "t3", "t4", "t5", "t6"}; 103 104const int SyscallNumReg = ArgumentRegs[7]; 105const int SyscallArgumentRegs[] = {ArgumentRegs[0], ArgumentRegs[1], 106 ArgumentRegs[2], ArgumentRegs[3]}; 107const int SyscallPseudoReturnReg = ReturnValueRegs[0]; 108 | 1/* 2 * Copyright (c) 2013 ARM Limited 3 * Copyright (c) 2014-2015 Sven Karlsson 4 * All rights reserved 5 * 6 * The license below extends only to copyright in the software and shall 7 * not be construed as granting a license to any other intellectual 8 * property including but not limited to intellectual property relating --- 92 unchanged lines hidden (view full) --- 101 "s8", "s9", "s10", "s11", 102 "t3", "t4", "t5", "t6"}; 103 104const int SyscallNumReg = ArgumentRegs[7]; 105const int SyscallArgumentRegs[] = {ArgumentRegs[0], ArgumentRegs[1], 106 ArgumentRegs[2], ArgumentRegs[3]}; 107const int SyscallPseudoReturnReg = ReturnValueRegs[0]; 108 |
109const int NumHpmcounter = 29; 110const int NumHpmcounterh = 29; 111const int NumMhpmcounter = 29; 112const int NumMhpmevent = 29; |
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109enum MiscRegIndex { | 113enum MiscRegIndex { |
114 MISCREG_USTATUS = 0x000, 115 MISCREG_UIE = 0x004, 116 MISCREG_UTVEC = 0x005, 117 MISCREG_USCRATCH = 0x040, 118 MISCREG_UEPC = 0x041, 119 MISCREG_UCAUSE = 0x042, 120 MISCREG_UBADADDR = 0x043, 121 MISCREG_UIP = 0x044, |
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110 MISCREG_FFLAGS = 0x001, 111 MISCREG_FRM = 0x002, 112 MISCREG_FCSR = 0x003, 113 MISCREG_CYCLE = 0xC00, 114 MISCREG_TIME = 0xC01, 115 MISCREG_INSTRET = 0xC02, | 122 MISCREG_FFLAGS = 0x001, 123 MISCREG_FRM = 0x002, 124 MISCREG_FCSR = 0x003, 125 MISCREG_CYCLE = 0xC00, 126 MISCREG_TIME = 0xC01, 127 MISCREG_INSTRET = 0xC02, |
128 MISCREG_HPMCOUNTER_BASE = 0xC03, |
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116 MISCREG_CYCLEH = 0xC80, 117 MISCREG_TIMEH = 0xC81, 118 MISCREG_INSTRETH = 0xC82, | 129 MISCREG_CYCLEH = 0xC80, 130 MISCREG_TIMEH = 0xC81, 131 MISCREG_INSTRETH = 0xC82, |
132 MISCREG_HPMCOUNTERH_BASE = 0xC83, |
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119 120 MISCREG_SSTATUS = 0x100, | 133 134 MISCREG_SSTATUS = 0x100, |
121 MISCREG_STVEC = 0x101, | 135 MISCREG_SEDELEG = 0x102, 136 MISCREG_SIDELEG = 0x103, |
122 MISCREG_SIE = 0x104, | 137 MISCREG_SIE = 0x104, |
123 MISCREG_STIMECMP = 0x121, 124 MISCREG_STIME = 0xD01, 125 MISCREG_STIMEH = 0xD81, | 138 MISCREG_STVEC = 0x105, |
126 MISCREG_SSCRATCH = 0x140, 127 MISCREG_SEPC = 0x141, | 139 MISCREG_SSCRATCH = 0x140, 140 MISCREG_SEPC = 0x141, |
128 MISCREG_SCAUSE = 0xD42, 129 MISCREG_SBADADDR = 0xD43, | 141 MISCREG_SCAUSE = 0x142, 142 MISCREG_SBADADDR = 0x143, |
130 MISCREG_SIP = 0x144, 131 MISCREG_SPTBR = 0x180, | 143 MISCREG_SIP = 0x144, 144 MISCREG_SPTBR = 0x180, |
132 MISCREG_SASID = 0x181, 133 MISCREG_CYCLEW = 0x900, 134 MISCREG_TIMEW = 0x901, 135 MISCREG_INSTRETW = 0x902, 136 MISCREG_CYCLEHW = 0x980, 137 MISCREG_TIMEHW = 0x981, 138 MISCREG_INSTRETHW = 0x982, | |
139 140 MISCREG_HSTATUS = 0x200, | 145 146 MISCREG_HSTATUS = 0x200, |
141 MISCREG_HTVEC = 0x201, 142 MISCREG_HTDELEG = 0x202, 143 MISCREG_HTIMECMP = 0x221, 144 MISCREG_HTIME = 0xE01, 145 MISCREG_HTIMEH = 0xE81, | 147 MISCREG_HEDELEG = 0x202, 148 MISCREG_HIDELEG = 0x203, 149 MISCREG_HIE = 0x204, 150 MISCREG_HTVEC = 0x205, |
146 MISCREG_HSCRATCH = 0x240, 147 MISCREG_HEPC = 0x241, 148 MISCREG_HCAUSE = 0x242, 149 MISCREG_HBADADDR = 0x243, | 151 MISCREG_HSCRATCH = 0x240, 152 MISCREG_HEPC = 0x241, 153 MISCREG_HCAUSE = 0x242, 154 MISCREG_HBADADDR = 0x243, |
150 MISCREG_STIMEW = 0xA01, 151 MISCREG_STIMEHW = 0xA81, | 155 MISCREG_HIP = 0x244, |
152 | 156 |
153 MISCREG_MCPUID = 0xF00, 154 MISCREG_MIMPID = 0xF01, 155 MISCREG_MHARTID = 0xF10, | 157 MISCREG_MVENDORID = 0xF11, 158 MISCREG_MARCHID = 0xF12, 159 MISCREG_MIMPID = 0xF13, 160 MISCREG_MHARTID = 0xF14, |
156 MISCREG_MSTATUS = 0x300, | 161 MISCREG_MSTATUS = 0x300, |
157 MISCREG_MTVEC = 0x301, 158 MISCREG_MTDELEG = 0x302, | 162 MISCREG_MISA = 0x301, 163 MISCREG_MEDELEG = 0x302, 164 MISCREG_MIDELEG = 0x303, |
159 MISCREG_MIE = 0x304, | 165 MISCREG_MIE = 0x304, |
160 MISCREG_MTIMECMP = 0x321, 161 MISCREG_MTIME = 0x701, 162 MISCREG_MTIMEH = 0x741, | 166 MISCREG_MTVEC = 0x305, |
163 MISCREG_MSCRATCH = 0x340, 164 MISCREG_MEPC = 0x341, 165 MISCREG_MCAUSE = 0x342, 166 MISCREG_MBADADDR = 0x343, 167 MISCREG_MIP = 0x344, 168 MISCREG_MBASE = 0x380, 169 MISCREG_MBOUND = 0x381, 170 MISCREG_MIBASE = 0x382, 171 MISCREG_MIBOUND = 0x383, 172 MISCREG_MDBASE = 0x384, 173 MISCREG_MDBOUND = 0x385, | 167 MISCREG_MSCRATCH = 0x340, 168 MISCREG_MEPC = 0x341, 169 MISCREG_MCAUSE = 0x342, 170 MISCREG_MBADADDR = 0x343, 171 MISCREG_MIP = 0x344, 172 MISCREG_MBASE = 0x380, 173 MISCREG_MBOUND = 0x381, 174 MISCREG_MIBASE = 0x382, 175 MISCREG_MIBOUND = 0x383, 176 MISCREG_MDBASE = 0x384, 177 MISCREG_MDBOUND = 0x385, |
174 MISCREG_HTIMEW = 0xB01, 175 MISCREG_HTIMEHW = 0xB81, 176 MISCREG_MTOHOST = 0x780, 177 MISCREG_MFROMHOST = 0x781 | 178 MISCREG_MCYCLE = 0xB00, 179 MISCREG_MINSTRET = 0xB02, 180 MISCREG_MHPMCOUNTER_BASE = 0xB03, 181 MISCREG_MUCOUNTEREN = 0x320, 182 MISCREG_MSCOUNTEREN = 0x321, 183 MISCREG_MHCOUNTEREN = 0x322, 184 MISCREG_MHPMEVENT_BASE = 0x323, 185 186 MISCREG_TSELECT = 0x7A0, 187 MISCREG_TDATA1 = 0x7A1, 188 MISCREG_TDATA2 = 0x7A2, 189 MISCREG_TDATA3 = 0x7A3, 190 MISCREG_DCSR = 0x7B0, 191 MISCREG_DPC = 0x7B1, 192 MISCREG_DSCRATCH = 0x7B2 |
178}; 179 180} 181 182#endif // __ARCH_RISCV_REGISTERS_HH__ | 193}; 194 195} 196 197#endif // __ARCH_RISCV_REGISTERS_HH__ |