registers.hh (11725:eb58f1bbeac8) registers.hh (11726:11950d45640b)
1/*
2 * Copyright (c) 2013 ARM Limited
3 * Copyright (c) 2014-2015 Sven Karlsson
4 * All rights reserved
5 *
6 * The license below extends only to copyright in the software and shall
7 * not be construed as granting a license to any other intellectual
8 * property including but not limited to intellectual property relating

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63typedef uint_fast16_t RegIndex;
64typedef uint64_t IntReg;
65typedef uint64_t FloatRegBits;
66typedef double FloatReg;
67typedef uint8_t CCReg; // Not applicable to Riscv
68typedef uint64_t MiscReg;
69
70const int NumIntArchRegs = 32;
1/*
2 * Copyright (c) 2013 ARM Limited
3 * Copyright (c) 2014-2015 Sven Karlsson
4 * All rights reserved
5 *
6 * The license below extends only to copyright in the software and shall
7 * not be construed as granting a license to any other intellectual
8 * property including but not limited to intellectual property relating

--- 54 unchanged lines hidden (view full) ---

63typedef uint_fast16_t RegIndex;
64typedef uint64_t IntReg;
65typedef uint64_t FloatRegBits;
66typedef double FloatReg;
67typedef uint8_t CCReg; // Not applicable to Riscv
68typedef uint64_t MiscReg;
69
70const int NumIntArchRegs = 32;
71const int NumIntRegs = NumIntArchRegs;
71const int NumMicroIntRegs = 1;
72const int NumIntRegs = NumIntArchRegs + NumMicroIntRegs;
72const int NumFloatRegs = 32;
73const int NumCCRegs = 0;
74const int NumMiscRegs = 4096;
75
76// These help enumerate all the registers for dependence tracking.
77const int FP_Reg_Base = NumIntRegs;
78const int CC_Reg_Base = FP_Reg_Base + NumFloatRegs;
79const int Misc_Reg_Base = CC_Reg_Base + NumCCRegs;
80const int Max_Reg_Index = Misc_Reg_Base + NumMiscRegs;
81
73const int NumFloatRegs = 32;
74const int NumCCRegs = 0;
75const int NumMiscRegs = 4096;
76
77// These help enumerate all the registers for dependence tracking.
78const int FP_Reg_Base = NumIntRegs;
79const int CC_Reg_Base = FP_Reg_Base + NumFloatRegs;
80const int Misc_Reg_Base = CC_Reg_Base + NumCCRegs;
81const int Max_Reg_Index = Misc_Reg_Base + NumMiscRegs;
82
82
83// Semantically meaningful register indices
84const int ZeroReg = 0;
85const int ReturnAddrReg = 1;
86const int StackPointerReg = 2;
87const int GlobalPointerReg = 3;
88const int ThreadPointerReg = 4;
89const int FramePointerReg = 8;
90const int ReturnValueRegs[] = {10, 11};
91const int ReturnValueReg = ReturnValueRegs[0];
92const int ArgumentRegs[] = {10, 11, 12, 13, 14, 15, 16, 17};
83// Semantically meaningful register indices
84const int ZeroReg = 0;
85const int ReturnAddrReg = 1;
86const int StackPointerReg = 2;
87const int GlobalPointerReg = 3;
88const int ThreadPointerReg = 4;
89const int FramePointerReg = 8;
90const int ReturnValueRegs[] = {10, 11};
91const int ReturnValueReg = ReturnValueRegs[0];
92const int ArgumentRegs[] = {10, 11, 12, 13, 14, 15, 16, 17};
93const int AMOTempReg = 32;
93
94const char* const RegisterNames[] = {"zero", "ra", "sp", "gp",
95 "tp", "t0", "t1", "t2",
96 "s0", "s1", "a0", "a1",
97 "a2", "a3", "a4", "a5",
98 "a6", "a7", "s2", "s3",
99 "s4", "s5", "s6", "s7",
100 "s8", "s9", "s10", "s11",

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95const char* const RegisterNames[] = {"zero", "ra", "sp", "gp",
96 "tp", "t0", "t1", "t2",
97 "s0", "s1", "a0", "a1",
98 "a2", "a3", "a4", "a5",
99 "a6", "a7", "s2", "s3",
100 "s4", "s5", "s6", "s7",
101 "s8", "s9", "s10", "s11",

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