68 69// Not applicable to RISC-V 70using VecElem = ::DummyVecElem; 71using VecReg = ::DummyVecReg; 72using ConstVecReg = ::DummyConstVecReg; 73using VecRegContainer = ::DummyVecRegContainer; 74constexpr unsigned NumVecElemPerVecReg = ::DummyNumVecElemPerVecReg; 75constexpr size_t VecRegSizeBytes = ::DummyVecRegSizeBytes; 76 77// Not applicable to RISC-V 78using VecPredReg = ::DummyVecPredReg; 79using ConstVecPredReg = ::DummyConstVecPredReg; 80using VecPredRegContainer = ::DummyVecPredRegContainer; 81constexpr size_t VecPredRegSizeBits = ::DummyVecPredRegSizeBits; 82constexpr bool VecPredRegHasPackedRepr = ::DummyVecPredRegHasPackedRepr; 83 84const int NumIntArchRegs = 32; 85const int NumMicroIntRegs = 1; 86const int NumIntRegs = NumIntArchRegs + NumMicroIntRegs; 87const int NumFloatRegs = 32; 88 89const unsigned NumVecRegs = 1; // Not applicable to RISC-V 90 // (1 to prevent warnings) 91const int NumVecPredRegs = 1; // Not applicable to RISC-V 92 // (1 to prevent warnings) 93 94const int NumCCRegs = 0; 95 96// Semantically meaningful register indices 97const int ZeroReg = 0; 98const int ReturnAddrReg = 1; 99const int StackPointerReg = 2; 100const int GlobalPointerReg = 3; 101const int ThreadPointerReg = 4; 102const int FramePointerReg = 8; 103const int ReturnValueReg = 10; 104const std::vector<int> ReturnValueRegs = {10, 11}; 105const std::vector<int> ArgumentRegs = {10, 11, 12, 13, 14, 15, 16, 17}; 106const int AMOTempReg = 32; 107 108const int SyscallPseudoReturnReg = 10; 109const std::vector<int> SyscallArgumentRegs = {10, 11, 12, 13, 14, 15, 16}; 110const int SyscallNumReg = 17; 111 112const std::vector<std::string> IntRegNames = { 113 "zero", "ra", "sp", "gp", 114 "tp", "t0", "t1", "t2", 115 "s0", "s1", "a0", "a1", 116 "a2", "a3", "a4", "a5", 117 "a6", "a7", "s2", "s3", 118 "s4", "s5", "s6", "s7", 119 "s8", "s9", "s10", "s11", 120 "t3", "t4", "t5", "t6" 121}; 122const std::vector<std::string> FloatRegNames = { 123 "ft0", "ft1", "ft2", "ft3", 124 "ft4", "ft5", "ft6", "ft7", 125 "fs0", "fs1", "fa0", "fa1", 126 "fa2", "fa3", "fa4", "fa5", 127 "fa6", "fa7", "fs2", "fs3", 128 "fs4", "fs5", "fs6", "fs7", 129 "fs8", "fs9", "fs10", "fs11", 130 "ft8", "ft9", "ft10", "ft11" 131}; 132 133enum MiscRegIndex { 134 MISCREG_PRV = 0, 135 MISCREG_ISA, 136 MISCREG_VENDORID, 137 MISCREG_ARCHID, 138 MISCREG_IMPID, 139 MISCREG_HARTID, 140 MISCREG_STATUS, 141 MISCREG_IP, 142 MISCREG_IE, 143 MISCREG_CYCLE, 144 MISCREG_TIME, 145 MISCREG_INSTRET, 146 MISCREG_HPMCOUNTER03, 147 MISCREG_HPMCOUNTER04, 148 MISCREG_HPMCOUNTER05, 149 MISCREG_HPMCOUNTER06, 150 MISCREG_HPMCOUNTER07, 151 MISCREG_HPMCOUNTER08, 152 MISCREG_HPMCOUNTER09, 153 MISCREG_HPMCOUNTER10, 154 MISCREG_HPMCOUNTER11, 155 MISCREG_HPMCOUNTER12, 156 MISCREG_HPMCOUNTER13, 157 MISCREG_HPMCOUNTER14, 158 MISCREG_HPMCOUNTER15, 159 MISCREG_HPMCOUNTER16, 160 MISCREG_HPMCOUNTER17, 161 MISCREG_HPMCOUNTER18, 162 MISCREG_HPMCOUNTER19, 163 MISCREG_HPMCOUNTER20, 164 MISCREG_HPMCOUNTER21, 165 MISCREG_HPMCOUNTER22, 166 MISCREG_HPMCOUNTER23, 167 MISCREG_HPMCOUNTER24, 168 MISCREG_HPMCOUNTER25, 169 MISCREG_HPMCOUNTER26, 170 MISCREG_HPMCOUNTER27, 171 MISCREG_HPMCOUNTER28, 172 MISCREG_HPMCOUNTER29, 173 MISCREG_HPMCOUNTER30, 174 MISCREG_HPMCOUNTER31, 175 MISCREG_HPMEVENT03, 176 MISCREG_HPMEVENT04, 177 MISCREG_HPMEVENT05, 178 MISCREG_HPMEVENT06, 179 MISCREG_HPMEVENT07, 180 MISCREG_HPMEVENT08, 181 MISCREG_HPMEVENT09, 182 MISCREG_HPMEVENT10, 183 MISCREG_HPMEVENT11, 184 MISCREG_HPMEVENT12, 185 MISCREG_HPMEVENT13, 186 MISCREG_HPMEVENT14, 187 MISCREG_HPMEVENT15, 188 MISCREG_HPMEVENT16, 189 MISCREG_HPMEVENT17, 190 MISCREG_HPMEVENT18, 191 MISCREG_HPMEVENT19, 192 MISCREG_HPMEVENT20, 193 MISCREG_HPMEVENT21, 194 MISCREG_HPMEVENT22, 195 MISCREG_HPMEVENT23, 196 MISCREG_HPMEVENT24, 197 MISCREG_HPMEVENT25, 198 MISCREG_HPMEVENT26, 199 MISCREG_HPMEVENT27, 200 MISCREG_HPMEVENT28, 201 MISCREG_HPMEVENT29, 202 MISCREG_HPMEVENT30, 203 MISCREG_HPMEVENT31, 204 MISCREG_TSELECT, 205 MISCREG_TDATA1, 206 MISCREG_TDATA2, 207 MISCREG_TDATA3, 208 MISCREG_DCSR, 209 MISCREG_DPC, 210 MISCREG_DSCRATCH, 211 212 MISCREG_MEDELEG, 213 MISCREG_MIDELEG, 214 MISCREG_MTVEC, 215 MISCREG_MCOUNTEREN, 216 MISCREG_MSCRATCH, 217 MISCREG_MEPC, 218 MISCREG_MCAUSE, 219 MISCREG_MTVAL, 220 MISCREG_PMPCFG0, 221 // pmpcfg1 rv32 only 222 MISCREG_PMPCFG2, 223 // pmpcfg3 rv32 only 224 MISCREG_PMPADDR00, 225 MISCREG_PMPADDR01, 226 MISCREG_PMPADDR02, 227 MISCREG_PMPADDR03, 228 MISCREG_PMPADDR04, 229 MISCREG_PMPADDR05, 230 MISCREG_PMPADDR06, 231 MISCREG_PMPADDR07, 232 MISCREG_PMPADDR08, 233 MISCREG_PMPADDR09, 234 MISCREG_PMPADDR10, 235 MISCREG_PMPADDR11, 236 MISCREG_PMPADDR12, 237 MISCREG_PMPADDR13, 238 MISCREG_PMPADDR14, 239 MISCREG_PMPADDR15, 240 241 MISCREG_SEDELEG, 242 MISCREG_SIDELEG, 243 MISCREG_STVEC, 244 MISCREG_SCOUNTEREN, 245 MISCREG_SSCRATCH, 246 MISCREG_SEPC, 247 MISCREG_SCAUSE, 248 MISCREG_STVAL, 249 MISCREG_SATP, 250 251 MISCREG_UTVEC, 252 MISCREG_USCRATCH, 253 MISCREG_UEPC, 254 MISCREG_UCAUSE, 255 MISCREG_UTVAL, 256 MISCREG_FFLAGS, 257 MISCREG_FRM, 258 259 NUM_MISCREGS 260}; 261const int NumMiscRegs = NUM_MISCREGS; 262 263enum CSRIndex { 264 CSR_USTATUS = 0x000, 265 CSR_UIE = 0x004, 266 CSR_UTVEC = 0x005, 267 CSR_USCRATCH = 0x040, 268 CSR_UEPC = 0x041, 269 CSR_UCAUSE = 0x042, 270 CSR_UTVAL = 0x043, 271 CSR_UIP = 0x044, 272 CSR_FFLAGS = 0x001, 273 CSR_FRM = 0x002, 274 CSR_FCSR = 0x003, 275 CSR_CYCLE = 0xC00, 276 CSR_TIME = 0xC01, 277 CSR_INSTRET = 0xC02, 278 CSR_HPMCOUNTER03 = 0xC03, 279 CSR_HPMCOUNTER04 = 0xC04, 280 CSR_HPMCOUNTER05 = 0xC05, 281 CSR_HPMCOUNTER06 = 0xC06, 282 CSR_HPMCOUNTER07 = 0xC07, 283 CSR_HPMCOUNTER08 = 0xC08, 284 CSR_HPMCOUNTER09 = 0xC09, 285 CSR_HPMCOUNTER10 = 0xC0A, 286 CSR_HPMCOUNTER11 = 0xC0B, 287 CSR_HPMCOUNTER12 = 0xC0C, 288 CSR_HPMCOUNTER13 = 0xC0D, 289 CSR_HPMCOUNTER14 = 0xC0E, 290 CSR_HPMCOUNTER15 = 0xC0F, 291 CSR_HPMCOUNTER16 = 0xC10, 292 CSR_HPMCOUNTER17 = 0xC11, 293 CSR_HPMCOUNTER18 = 0xC12, 294 CSR_HPMCOUNTER19 = 0xC13, 295 CSR_HPMCOUNTER20 = 0xC14, 296 CSR_HPMCOUNTER21 = 0xC15, 297 CSR_HPMCOUNTER22 = 0xC16, 298 CSR_HPMCOUNTER23 = 0xC17, 299 CSR_HPMCOUNTER24 = 0xC18, 300 CSR_HPMCOUNTER25 = 0xC19, 301 CSR_HPMCOUNTER26 = 0xC1A, 302 CSR_HPMCOUNTER27 = 0xC1B, 303 CSR_HPMCOUNTER28 = 0xC1C, 304 CSR_HPMCOUNTER29 = 0xC1D, 305 CSR_HPMCOUNTER30 = 0xC1E, 306 CSR_HPMCOUNTER31 = 0xC1F, 307 // HPMCOUNTERH rv32 only 308 309 CSR_SSTATUS = 0x100, 310 CSR_SEDELEG = 0x102, 311 CSR_SIDELEG = 0x103, 312 CSR_SIE = 0x104, 313 CSR_STVEC = 0x105, 314 CSR_SSCRATCH = 0x140, 315 CSR_SEPC = 0x141, 316 CSR_SCAUSE = 0x142, 317 CSR_STVAL = 0x143, 318 CSR_SIP = 0x144, 319 CSR_SATP = 0x180, 320 321 CSR_MVENDORID = 0xF11, 322 CSR_MARCHID = 0xF12, 323 CSR_MIMPID = 0xF13, 324 CSR_MHARTID = 0xF14, 325 CSR_MSTATUS = 0x300, 326 CSR_MISA = 0x301, 327 CSR_MEDELEG = 0x302, 328 CSR_MIDELEG = 0x303, 329 CSR_MIE = 0x304, 330 CSR_MTVEC = 0x305, 331 CSR_MSCRATCH = 0x340, 332 CSR_MEPC = 0x341, 333 CSR_MCAUSE = 0x342, 334 CSR_MTVAL = 0x343, 335 CSR_MIP = 0x344, 336 CSR_PMPCFG0 = 0x3A0, 337 // pmpcfg1 rv32 only 338 CSR_PMPCFG2 = 0x3A2, 339 // pmpcfg3 rv32 only 340 CSR_PMPADDR00 = 0x3B0, 341 CSR_PMPADDR01 = 0x3B1, 342 CSR_PMPADDR02 = 0x3B2, 343 CSR_PMPADDR03 = 0x3B3, 344 CSR_PMPADDR04 = 0x3B4, 345 CSR_PMPADDR05 = 0x3B5, 346 CSR_PMPADDR06 = 0x3B6, 347 CSR_PMPADDR07 = 0x3B7, 348 CSR_PMPADDR08 = 0x3B8, 349 CSR_PMPADDR09 = 0x3B9, 350 CSR_PMPADDR10 = 0x3BA, 351 CSR_PMPADDR11 = 0x3BB, 352 CSR_PMPADDR12 = 0x3BC, 353 CSR_PMPADDR13 = 0x3BD, 354 CSR_PMPADDR14 = 0x3BE, 355 CSR_PMPADDR15 = 0x3BF, 356 CSR_MCYCLE = 0xB00, 357 CSR_MINSTRET = 0xB02, 358 CSR_MHPMCOUNTER03 = 0xC03, 359 CSR_MHPMCOUNTER04 = 0xC04, 360 CSR_MHPMCOUNTER05 = 0xC05, 361 CSR_MHPMCOUNTER06 = 0xC06, 362 CSR_MHPMCOUNTER07 = 0xC07, 363 CSR_MHPMCOUNTER08 = 0xC08, 364 CSR_MHPMCOUNTER09 = 0xC09, 365 CSR_MHPMCOUNTER10 = 0xC0A, 366 CSR_MHPMCOUNTER11 = 0xC0B, 367 CSR_MHPMCOUNTER12 = 0xC0C, 368 CSR_MHPMCOUNTER13 = 0xC0D, 369 CSR_MHPMCOUNTER14 = 0xC0E, 370 CSR_MHPMCOUNTER15 = 0xC0F, 371 CSR_MHPMCOUNTER16 = 0xC10, 372 CSR_MHPMCOUNTER17 = 0xC11, 373 CSR_MHPMCOUNTER18 = 0xC12, 374 CSR_MHPMCOUNTER19 = 0xC13, 375 CSR_MHPMCOUNTER20 = 0xC14, 376 CSR_MHPMCOUNTER21 = 0xC15, 377 CSR_MHPMCOUNTER22 = 0xC16, 378 CSR_MHPMCOUNTER23 = 0xC17, 379 CSR_MHPMCOUNTER24 = 0xC18, 380 CSR_MHPMCOUNTER25 = 0xC19, 381 CSR_MHPMCOUNTER26 = 0xC1A, 382 CSR_MHPMCOUNTER27 = 0xC1B, 383 CSR_MHPMCOUNTER28 = 0xC1C, 384 CSR_MHPMCOUNTER29 = 0xC1D, 385 CSR_MHPMCOUNTER30 = 0xC1E, 386 CSR_MHPMCOUNTER31 = 0xC1F, 387 // MHPMCOUNTERH rv32 only 388 CSR_MHPMEVENT03 = 0x323, 389 CSR_MHPMEVENT04 = 0x324, 390 CSR_MHPMEVENT05 = 0x325, 391 CSR_MHPMEVENT06 = 0x326, 392 CSR_MHPMEVENT07 = 0x327, 393 CSR_MHPMEVENT08 = 0x328, 394 CSR_MHPMEVENT09 = 0x329, 395 CSR_MHPMEVENT10 = 0x32A, 396 CSR_MHPMEVENT11 = 0x32B, 397 CSR_MHPMEVENT12 = 0x32C, 398 CSR_MHPMEVENT13 = 0x32D, 399 CSR_MHPMEVENT14 = 0x32E, 400 CSR_MHPMEVENT15 = 0x32F, 401 CSR_MHPMEVENT16 = 0x330, 402 CSR_MHPMEVENT17 = 0x331, 403 CSR_MHPMEVENT18 = 0x332, 404 CSR_MHPMEVENT19 = 0x333, 405 CSR_MHPMEVENT20 = 0x334, 406 CSR_MHPMEVENT21 = 0x335, 407 CSR_MHPMEVENT22 = 0x336, 408 CSR_MHPMEVENT23 = 0x337, 409 CSR_MHPMEVENT24 = 0x338, 410 CSR_MHPMEVENT25 = 0x339, 411 CSR_MHPMEVENT26 = 0x33A, 412 CSR_MHPMEVENT27 = 0x33B, 413 CSR_MHPMEVENT28 = 0x33C, 414 CSR_MHPMEVENT29 = 0x33D, 415 CSR_MHPMEVENT30 = 0x33E, 416 CSR_MHPMEVENT31 = 0x33F, 417 418 CSR_TSELECT = 0x7A0, 419 CSR_TDATA1 = 0x7A1, 420 CSR_TDATA2 = 0x7A2, 421 CSR_TDATA3 = 0x7A3, 422 CSR_DCSR = 0x7B0, 423 CSR_DPC = 0x7B1, 424 CSR_DSCRATCH = 0x7B2 425}; 426 427struct CSRMetadata 428{ 429 const std::string name; 430 const int physIndex; 431}; 432 433const std::map<int, CSRMetadata> CSRData = { 434 {CSR_USTATUS, {"ustatus", MISCREG_STATUS}}, 435 {CSR_UIE, {"uie", MISCREG_IE}}, 436 {CSR_UTVEC, {"utvec", MISCREG_UTVEC}}, 437 {CSR_USCRATCH, {"uscratch", MISCREG_USCRATCH}}, 438 {CSR_UEPC, {"uepc", MISCREG_UEPC}}, 439 {CSR_UCAUSE, {"ucause", MISCREG_UCAUSE}}, 440 {CSR_UTVAL, {"utval", MISCREG_UTVAL}}, 441 {CSR_UIP, {"uip", MISCREG_IP}}, 442 {CSR_FFLAGS, {"fflags", MISCREG_FFLAGS}}, 443 {CSR_FRM, {"frm", MISCREG_FRM}}, 444 {CSR_FCSR, {"fcsr", MISCREG_FFLAGS}}, // Actually FRM << 5 | FFLAGS 445 {CSR_CYCLE, {"cycle", MISCREG_CYCLE}}, 446 {CSR_TIME, {"time", MISCREG_TIME}}, 447 {CSR_INSTRET, {"instret", MISCREG_INSTRET}}, 448 {CSR_HPMCOUNTER03, {"hpmcounter03", MISCREG_HPMCOUNTER03}}, 449 {CSR_HPMCOUNTER04, {"hpmcounter04", MISCREG_HPMCOUNTER04}}, 450 {CSR_HPMCOUNTER05, {"hpmcounter05", MISCREG_HPMCOUNTER05}}, 451 {CSR_HPMCOUNTER06, {"hpmcounter06", MISCREG_HPMCOUNTER06}}, 452 {CSR_HPMCOUNTER07, {"hpmcounter07", MISCREG_HPMCOUNTER07}}, 453 {CSR_HPMCOUNTER08, {"hpmcounter08", MISCREG_HPMCOUNTER08}}, 454 {CSR_HPMCOUNTER09, {"hpmcounter09", MISCREG_HPMCOUNTER09}}, 455 {CSR_HPMCOUNTER10, {"hpmcounter10", MISCREG_HPMCOUNTER10}}, 456 {CSR_HPMCOUNTER11, {"hpmcounter11", MISCREG_HPMCOUNTER11}}, 457 {CSR_HPMCOUNTER12, {"hpmcounter12", MISCREG_HPMCOUNTER12}}, 458 {CSR_HPMCOUNTER13, {"hpmcounter13", MISCREG_HPMCOUNTER13}}, 459 {CSR_HPMCOUNTER14, {"hpmcounter14", MISCREG_HPMCOUNTER14}}, 460 {CSR_HPMCOUNTER15, {"hpmcounter15", MISCREG_HPMCOUNTER15}}, 461 {CSR_HPMCOUNTER16, {"hpmcounter16", MISCREG_HPMCOUNTER16}}, 462 {CSR_HPMCOUNTER17, {"hpmcounter17", MISCREG_HPMCOUNTER17}}, 463 {CSR_HPMCOUNTER18, {"hpmcounter18", MISCREG_HPMCOUNTER18}}, 464 {CSR_HPMCOUNTER19, {"hpmcounter19", MISCREG_HPMCOUNTER19}}, 465 {CSR_HPMCOUNTER20, {"hpmcounter20", MISCREG_HPMCOUNTER20}}, 466 {CSR_HPMCOUNTER21, {"hpmcounter21", MISCREG_HPMCOUNTER21}}, 467 {CSR_HPMCOUNTER22, {"hpmcounter22", MISCREG_HPMCOUNTER22}}, 468 {CSR_HPMCOUNTER23, {"hpmcounter23", MISCREG_HPMCOUNTER23}}, 469 {CSR_HPMCOUNTER24, {"hpmcounter24", MISCREG_HPMCOUNTER24}}, 470 {CSR_HPMCOUNTER25, {"hpmcounter25", MISCREG_HPMCOUNTER25}}, 471 {CSR_HPMCOUNTER26, {"hpmcounter26", MISCREG_HPMCOUNTER26}}, 472 {CSR_HPMCOUNTER27, {"hpmcounter27", MISCREG_HPMCOUNTER27}}, 473 {CSR_HPMCOUNTER28, {"hpmcounter28", MISCREG_HPMCOUNTER28}}, 474 {CSR_HPMCOUNTER29, {"hpmcounter29", MISCREG_HPMCOUNTER29}}, 475 {CSR_HPMCOUNTER30, {"hpmcounter30", MISCREG_HPMCOUNTER30}}, 476 {CSR_HPMCOUNTER31, {"hpmcounter31", MISCREG_HPMCOUNTER31}}, 477 478 {CSR_SSTATUS, {"sstatus", MISCREG_STATUS}}, 479 {CSR_SEDELEG, {"sedeleg", MISCREG_SEDELEG}}, 480 {CSR_SIDELEG, {"sideleg", MISCREG_SIDELEG}}, 481 {CSR_SIE, {"sie", MISCREG_IE}}, 482 {CSR_STVEC, {"stvec", MISCREG_STVEC}}, 483 {CSR_SSCRATCH, {"sscratch", MISCREG_SSCRATCH}}, 484 {CSR_SEPC, {"sepc", MISCREG_SEPC}}, 485 {CSR_SCAUSE, {"scause", MISCREG_SCAUSE}}, 486 {CSR_STVAL, {"stval", MISCREG_STVAL}}, 487 {CSR_SIP, {"sip", MISCREG_IP}}, 488 {CSR_SATP, {"satp", MISCREG_SATP}}, 489 490 {CSR_MVENDORID, {"mvendorid", MISCREG_VENDORID}}, 491 {CSR_MARCHID, {"marchid", MISCREG_ARCHID}}, 492 {CSR_MIMPID, {"mimpid", MISCREG_IMPID}}, 493 {CSR_MHARTID, {"mhartid", MISCREG_HARTID}}, 494 {CSR_MSTATUS, {"mstatus", MISCREG_STATUS}}, 495 {CSR_MISA, {"misa", MISCREG_ISA}}, 496 {CSR_MEDELEG, {"medeleg", MISCREG_MEDELEG}}, 497 {CSR_MIDELEG, {"mideleg", MISCREG_MIDELEG}}, 498 {CSR_MIE, {"mie", MISCREG_IE}}, 499 {CSR_MTVEC, {"mtvec", MISCREG_MTVEC}}, 500 {CSR_MSCRATCH, {"mscratch", MISCREG_MSCRATCH}}, 501 {CSR_MEPC, {"mepc", MISCREG_MEPC}}, 502 {CSR_MCAUSE, {"mcause", MISCREG_MCAUSE}}, 503 {CSR_MTVAL, {"mtval", MISCREG_MTVAL}}, 504 {CSR_MIP, {"mip", MISCREG_IP}}, 505 {CSR_PMPCFG0, {"pmpcfg0", MISCREG_PMPCFG0}}, 506 // pmpcfg1 rv32 only 507 {CSR_PMPCFG2, {"pmpcfg2", MISCREG_PMPCFG2}}, 508 // pmpcfg3 rv32 only 509 {CSR_PMPADDR00, {"pmpaddr0", MISCREG_PMPADDR00}}, 510 {CSR_PMPADDR01, {"pmpaddr1", MISCREG_PMPADDR01}}, 511 {CSR_PMPADDR02, {"pmpaddr2", MISCREG_PMPADDR02}}, 512 {CSR_PMPADDR03, {"pmpaddr3", MISCREG_PMPADDR03}}, 513 {CSR_PMPADDR04, {"pmpaddr4", MISCREG_PMPADDR04}}, 514 {CSR_PMPADDR05, {"pmpaddr5", MISCREG_PMPADDR05}}, 515 {CSR_PMPADDR06, {"pmpaddr6", MISCREG_PMPADDR06}}, 516 {CSR_PMPADDR07, {"pmpaddr7", MISCREG_PMPADDR07}}, 517 {CSR_PMPADDR08, {"pmpaddr8", MISCREG_PMPADDR08}}, 518 {CSR_PMPADDR09, {"pmpaddr9", MISCREG_PMPADDR09}}, 519 {CSR_PMPADDR10, {"pmpaddr10", MISCREG_PMPADDR10}}, 520 {CSR_PMPADDR11, {"pmpaddr11", MISCREG_PMPADDR11}}, 521 {CSR_PMPADDR12, {"pmpaddr12", MISCREG_PMPADDR12}}, 522 {CSR_PMPADDR13, {"pmpaddr13", MISCREG_PMPADDR13}}, 523 {CSR_PMPADDR14, {"pmpaddr14", MISCREG_PMPADDR14}}, 524 {CSR_PMPADDR15, {"pmpaddr15", MISCREG_PMPADDR15}}, 525 {CSR_MCYCLE, {"mcycle", MISCREG_CYCLE}}, 526 {CSR_MINSTRET, {"minstret", MISCREG_INSTRET}}, 527 {CSR_MHPMCOUNTER03, {"mhpmcounter03", MISCREG_HPMCOUNTER03}}, 528 {CSR_MHPMCOUNTER04, {"mhpmcounter04", MISCREG_HPMCOUNTER04}}, 529 {CSR_MHPMCOUNTER05, {"mhpmcounter05", MISCREG_HPMCOUNTER05}}, 530 {CSR_MHPMCOUNTER06, {"mhpmcounter06", MISCREG_HPMCOUNTER06}}, 531 {CSR_MHPMCOUNTER07, {"mhpmcounter07", MISCREG_HPMCOUNTER07}}, 532 {CSR_MHPMCOUNTER08, {"mhpmcounter08", MISCREG_HPMCOUNTER08}}, 533 {CSR_MHPMCOUNTER09, {"mhpmcounter09", MISCREG_HPMCOUNTER09}}, 534 {CSR_MHPMCOUNTER10, {"mhpmcounter10", MISCREG_HPMCOUNTER10}}, 535 {CSR_MHPMCOUNTER11, {"mhpmcounter11", MISCREG_HPMCOUNTER11}}, 536 {CSR_MHPMCOUNTER12, {"mhpmcounter12", MISCREG_HPMCOUNTER12}}, 537 {CSR_MHPMCOUNTER13, {"mhpmcounter13", MISCREG_HPMCOUNTER13}}, 538 {CSR_MHPMCOUNTER14, {"mhpmcounter14", MISCREG_HPMCOUNTER14}}, 539 {CSR_MHPMCOUNTER15, {"mhpmcounter15", MISCREG_HPMCOUNTER15}}, 540 {CSR_MHPMCOUNTER16, {"mhpmcounter16", MISCREG_HPMCOUNTER16}}, 541 {CSR_MHPMCOUNTER17, {"mhpmcounter17", MISCREG_HPMCOUNTER17}}, 542 {CSR_MHPMCOUNTER18, {"mhpmcounter18", MISCREG_HPMCOUNTER18}}, 543 {CSR_MHPMCOUNTER19, {"mhpmcounter19", MISCREG_HPMCOUNTER19}}, 544 {CSR_MHPMCOUNTER20, {"mhpmcounter20", MISCREG_HPMCOUNTER20}}, 545 {CSR_MHPMCOUNTER21, {"mhpmcounter21", MISCREG_HPMCOUNTER21}}, 546 {CSR_MHPMCOUNTER22, {"mhpmcounter22", MISCREG_HPMCOUNTER22}}, 547 {CSR_MHPMCOUNTER23, {"mhpmcounter23", MISCREG_HPMCOUNTER23}}, 548 {CSR_MHPMCOUNTER24, {"mhpmcounter24", MISCREG_HPMCOUNTER24}}, 549 {CSR_MHPMCOUNTER25, {"mhpmcounter25", MISCREG_HPMCOUNTER25}}, 550 {CSR_MHPMCOUNTER26, {"mhpmcounter26", MISCREG_HPMCOUNTER26}}, 551 {CSR_MHPMCOUNTER27, {"mhpmcounter27", MISCREG_HPMCOUNTER27}}, 552 {CSR_MHPMCOUNTER28, {"mhpmcounter28", MISCREG_HPMCOUNTER28}}, 553 {CSR_MHPMCOUNTER29, {"mhpmcounter29", MISCREG_HPMCOUNTER29}}, 554 {CSR_MHPMCOUNTER30, {"mhpmcounter30", MISCREG_HPMCOUNTER30}}, 555 {CSR_MHPMCOUNTER31, {"mhpmcounter31", MISCREG_HPMCOUNTER31}}, 556 {CSR_MHPMEVENT03, {"mhpmevent03", MISCREG_HPMEVENT03}}, 557 {CSR_MHPMEVENT04, {"mhpmevent04", MISCREG_HPMEVENT04}}, 558 {CSR_MHPMEVENT05, {"mhpmevent05", MISCREG_HPMEVENT05}}, 559 {CSR_MHPMEVENT06, {"mhpmevent06", MISCREG_HPMEVENT06}}, 560 {CSR_MHPMEVENT07, {"mhpmevent07", MISCREG_HPMEVENT07}}, 561 {CSR_MHPMEVENT08, {"mhpmevent08", MISCREG_HPMEVENT08}}, 562 {CSR_MHPMEVENT09, {"mhpmevent09", MISCREG_HPMEVENT09}}, 563 {CSR_MHPMEVENT10, {"mhpmevent10", MISCREG_HPMEVENT10}}, 564 {CSR_MHPMEVENT11, {"mhpmevent11", MISCREG_HPMEVENT11}}, 565 {CSR_MHPMEVENT12, {"mhpmevent12", MISCREG_HPMEVENT12}}, 566 {CSR_MHPMEVENT13, {"mhpmevent13", MISCREG_HPMEVENT13}}, 567 {CSR_MHPMEVENT14, {"mhpmevent14", MISCREG_HPMEVENT14}}, 568 {CSR_MHPMEVENT15, {"mhpmevent15", MISCREG_HPMEVENT15}}, 569 {CSR_MHPMEVENT16, {"mhpmevent16", MISCREG_HPMEVENT16}}, 570 {CSR_MHPMEVENT17, {"mhpmevent17", MISCREG_HPMEVENT17}}, 571 {CSR_MHPMEVENT18, {"mhpmevent18", MISCREG_HPMEVENT18}}, 572 {CSR_MHPMEVENT19, {"mhpmevent19", MISCREG_HPMEVENT19}}, 573 {CSR_MHPMEVENT20, {"mhpmevent20", MISCREG_HPMEVENT20}}, 574 {CSR_MHPMEVENT21, {"mhpmevent21", MISCREG_HPMEVENT21}}, 575 {CSR_MHPMEVENT22, {"mhpmevent22", MISCREG_HPMEVENT22}}, 576 {CSR_MHPMEVENT23, {"mhpmevent23", MISCREG_HPMEVENT23}}, 577 {CSR_MHPMEVENT24, {"mhpmevent24", MISCREG_HPMEVENT24}}, 578 {CSR_MHPMEVENT25, {"mhpmevent25", MISCREG_HPMEVENT25}}, 579 {CSR_MHPMEVENT26, {"mhpmevent26", MISCREG_HPMEVENT26}}, 580 {CSR_MHPMEVENT27, {"mhpmevent27", MISCREG_HPMEVENT27}}, 581 {CSR_MHPMEVENT28, {"mhpmevent28", MISCREG_HPMEVENT28}}, 582 {CSR_MHPMEVENT29, {"mhpmevent29", MISCREG_HPMEVENT29}}, 583 {CSR_MHPMEVENT30, {"mhpmevent30", MISCREG_HPMEVENT30}}, 584 {CSR_MHPMEVENT31, {"mhpmevent31", MISCREG_HPMEVENT31}}, 585 586 {CSR_TSELECT, {"tselect", MISCREG_TSELECT}}, 587 {CSR_TDATA1, {"tdata1", MISCREG_TDATA1}}, 588 {CSR_TDATA2, {"tdata2", MISCREG_TDATA2}}, 589 {CSR_TDATA3, {"tdata3", MISCREG_TDATA3}}, 590 {CSR_DCSR, {"dcsr", MISCREG_DCSR}}, 591 {CSR_DPC, {"dpc", MISCREG_DPC}}, 592 {CSR_DSCRATCH, {"dscratch", MISCREG_DSCRATCH}} 593}; 594 595/** 596 * These fields are specified in the RISC-V Instruction Set Manual, Volume II, 597 * v1.10, accessible at www.riscv.org. in Figure 3.7. The main register that 598 * uses these fields is the MSTATUS register, which is shadowed by two others 599 * accessible at lower privilege levels (SSTATUS and USTATUS) that can't see 600 * the fields for higher privileges. 601 */ 602BitUnion64(STATUS) 603 Bitfield<63> sd; 604 Bitfield<35, 34> sxl; 605 Bitfield<33, 32> uxl; 606 Bitfield<22> tsr; 607 Bitfield<21> tw; 608 Bitfield<20> tvm; 609 Bitfield<19> mxr; 610 Bitfield<18> sum; 611 Bitfield<17> mprv; 612 Bitfield<16, 15> xs; 613 Bitfield<14, 13> fs; 614 Bitfield<12, 11> mpp; 615 Bitfield<8> spp; 616 Bitfield<7> mpie; 617 Bitfield<5> spie; 618 Bitfield<4> upie; 619 Bitfield<3> mie; 620 Bitfield<1> sie; 621 Bitfield<0> uie; 622EndBitUnion(STATUS) 623 624/** 625 * These fields are specified in the RISC-V Instruction Set Manual, Volume II, 626 * v1.10 in Figures 3.11 and 3.12, accessible at www.riscv.org. Both the MIP 627 * and MIE registers have the same fields, so accesses to either should use 628 * this bit union. 629 */ 630BitUnion64(INTERRUPT) 631 Bitfield<11> mei; 632 Bitfield<9> sei; 633 Bitfield<8> uei; 634 Bitfield<7> mti; 635 Bitfield<5> sti; 636 Bitfield<4> uti; 637 Bitfield<3> msi; 638 Bitfield<1> ssi; 639 Bitfield<0> usi; 640EndBitUnion(INTERRUPT) 641
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