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< typedef RegVal IntReg;
< typedef RegVal FloatReg;
70d67
< typedef RegVal MiscReg;
645c642
< const off_t MXL_OFFSET = (sizeof(MiscReg) * 8 - 2);
---
> const off_t MXL_OFFSET = (sizeof(uint64_t) * 8 - 2);
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< const MiscReg ISA_MXL_MASK = 3ULL << MXL_OFFSET;
< const MiscReg ISA_EXT_MASK = mask(26);
< const MiscReg MISA_MASK = ISA_MXL_MASK | ISA_EXT_MASK;
---
> const RegVal ISA_MXL_MASK = 3ULL << MXL_OFFSET;
> const RegVal ISA_EXT_MASK = mask(26);
> const RegVal MISA_MASK = ISA_MXL_MASK | ISA_EXT_MASK;
655,693c652,690
< const MiscReg STATUS_SD_MASK = 1ULL << ((sizeof(MiscReg) * 8) - 1);
< const MiscReg STATUS_SXL_MASK = 3ULL << SXL_OFFSET;
< const MiscReg STATUS_UXL_MASK = 3ULL << UXL_OFFSET;
< const MiscReg STATUS_TSR_MASK = 1ULL << 22;
< const MiscReg STATUS_TW_MASK = 1ULL << 21;
< const MiscReg STATUS_TVM_MASK = 1ULL << 20;
< const MiscReg STATUS_MXR_MASK = 1ULL << 19;
< const MiscReg STATUS_SUM_MASK = 1ULL << 18;
< const MiscReg STATUS_MPRV_MASK = 1ULL << 17;
< const MiscReg STATUS_XS_MASK = 3ULL << 15;
< const MiscReg STATUS_FS_MASK = 3ULL << FS_OFFSET;
< const MiscReg STATUS_MPP_MASK = 3ULL << 11;
< const MiscReg STATUS_SPP_MASK = 1ULL << 8;
< const MiscReg STATUS_MPIE_MASK = 1ULL << 7;
< const MiscReg STATUS_SPIE_MASK = 1ULL << 5;
< const MiscReg STATUS_UPIE_MASK = 1ULL << 4;
< const MiscReg STATUS_MIE_MASK = 1ULL << 3;
< const MiscReg STATUS_SIE_MASK = 1ULL << 1;
< const MiscReg STATUS_UIE_MASK = 1ULL << 0;
< const MiscReg MSTATUS_MASK = STATUS_SD_MASK | STATUS_SXL_MASK |
< STATUS_UXL_MASK | STATUS_TSR_MASK |
< STATUS_TW_MASK | STATUS_TVM_MASK |
< STATUS_MXR_MASK | STATUS_SUM_MASK |
< STATUS_MPRV_MASK | STATUS_XS_MASK |
< STATUS_FS_MASK | STATUS_MPP_MASK |
< STATUS_SPP_MASK | STATUS_MPIE_MASK |
< STATUS_SPIE_MASK | STATUS_UPIE_MASK |
< STATUS_MIE_MASK | STATUS_SIE_MASK |
< STATUS_UIE_MASK;
< const MiscReg SSTATUS_MASK = STATUS_SD_MASK | STATUS_UXL_MASK |
< STATUS_MXR_MASK | STATUS_SUM_MASK |
< STATUS_XS_MASK | STATUS_FS_MASK |
< STATUS_SPP_MASK | STATUS_SPIE_MASK |
< STATUS_UPIE_MASK | STATUS_SIE_MASK |
< STATUS_UIE_MASK;
< const MiscReg USTATUS_MASK = STATUS_SD_MASK | STATUS_MXR_MASK |
< STATUS_SUM_MASK | STATUS_XS_MASK |
< STATUS_FS_MASK | STATUS_UPIE_MASK |
< STATUS_UIE_MASK;
---
> const RegVal STATUS_SD_MASK = 1ULL << ((sizeof(uint64_t) * 8) - 1);
> const RegVal STATUS_SXL_MASK = 3ULL << SXL_OFFSET;
> const RegVal STATUS_UXL_MASK = 3ULL << UXL_OFFSET;
> const RegVal STATUS_TSR_MASK = 1ULL << 22;
> const RegVal STATUS_TW_MASK = 1ULL << 21;
> const RegVal STATUS_TVM_MASK = 1ULL << 20;
> const RegVal STATUS_MXR_MASK = 1ULL << 19;
> const RegVal STATUS_SUM_MASK = 1ULL << 18;
> const RegVal STATUS_MPRV_MASK = 1ULL << 17;
> const RegVal STATUS_XS_MASK = 3ULL << 15;
> const RegVal STATUS_FS_MASK = 3ULL << FS_OFFSET;
> const RegVal STATUS_MPP_MASK = 3ULL << 11;
> const RegVal STATUS_SPP_MASK = 1ULL << 8;
> const RegVal STATUS_MPIE_MASK = 1ULL << 7;
> const RegVal STATUS_SPIE_MASK = 1ULL << 5;
> const RegVal STATUS_UPIE_MASK = 1ULL << 4;
> const RegVal STATUS_MIE_MASK = 1ULL << 3;
> const RegVal STATUS_SIE_MASK = 1ULL << 1;
> const RegVal STATUS_UIE_MASK = 1ULL << 0;
> const RegVal MSTATUS_MASK = STATUS_SD_MASK | STATUS_SXL_MASK |
> STATUS_UXL_MASK | STATUS_TSR_MASK |
> STATUS_TW_MASK | STATUS_TVM_MASK |
> STATUS_MXR_MASK | STATUS_SUM_MASK |
> STATUS_MPRV_MASK | STATUS_XS_MASK |
> STATUS_FS_MASK | STATUS_MPP_MASK |
> STATUS_SPP_MASK | STATUS_MPIE_MASK |
> STATUS_SPIE_MASK | STATUS_UPIE_MASK |
> STATUS_MIE_MASK | STATUS_SIE_MASK |
> STATUS_UIE_MASK;
> const RegVal SSTATUS_MASK = STATUS_SD_MASK | STATUS_UXL_MASK |
> STATUS_MXR_MASK | STATUS_SUM_MASK |
> STATUS_XS_MASK | STATUS_FS_MASK |
> STATUS_SPP_MASK | STATUS_SPIE_MASK |
> STATUS_UPIE_MASK | STATUS_SIE_MASK |
> STATUS_UIE_MASK;
> const RegVal USTATUS_MASK = STATUS_SD_MASK | STATUS_MXR_MASK |
> STATUS_SUM_MASK | STATUS_XS_MASK |
> STATUS_FS_MASK | STATUS_UPIE_MASK |
> STATUS_UIE_MASK;
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< const MiscReg MEI_MASK = 1ULL << 11;
< const MiscReg SEI_MASK = 1ULL << 9;
< const MiscReg UEI_MASK = 1ULL << 8;
< const MiscReg MTI_MASK = 1ULL << 7;
< const MiscReg STI_MASK = 1ULL << 5;
< const MiscReg UTI_MASK = 1ULL << 4;
< const MiscReg MSI_MASK = 1ULL << 3;
< const MiscReg SSI_MASK = 1ULL << 1;
< const MiscReg USI_MASK = 1ULL << 0;
< const MiscReg MI_MASK = MEI_MASK | SEI_MASK | UEI_MASK |
< MTI_MASK | STI_MASK | UTI_MASK |
< MSI_MASK | SSI_MASK | USI_MASK;
< const MiscReg SI_MASK = SEI_MASK | UEI_MASK |
< STI_MASK | UTI_MASK |
< SSI_MASK | USI_MASK;
< const MiscReg UI_MASK = UEI_MASK | UTI_MASK | USI_MASK;
< const MiscReg FFLAGS_MASK = (1 << FRM_OFFSET) - 1;
< const MiscReg FRM_MASK = 0x7;
---
> const RegVal MEI_MASK = 1ULL << 11;
> const RegVal SEI_MASK = 1ULL << 9;
> const RegVal UEI_MASK = 1ULL << 8;
> const RegVal MTI_MASK = 1ULL << 7;
> const RegVal STI_MASK = 1ULL << 5;
> const RegVal UTI_MASK = 1ULL << 4;
> const RegVal MSI_MASK = 1ULL << 3;
> const RegVal SSI_MASK = 1ULL << 1;
> const RegVal USI_MASK = 1ULL << 0;
> const RegVal MI_MASK = MEI_MASK | SEI_MASK | UEI_MASK |
> MTI_MASK | STI_MASK | UTI_MASK |
> MSI_MASK | SSI_MASK | USI_MASK;
> const RegVal SI_MASK = SEI_MASK | UEI_MASK |
> STI_MASK | UTI_MASK |
> SSI_MASK | USI_MASK;
> const RegVal UI_MASK = UEI_MASK | UTI_MASK | USI_MASK;
> const RegVal FFLAGS_MASK = (1 << FRM_OFFSET) - 1;
> const RegVal FRM_MASK = 0x7;
714c711
< const std::map<int, MiscReg> CSRMasks = {
---
> const std::map<int, RegVal> CSRMasks = {