1/* 2 * Copyright (c) 2013 ARM Limited 3 * Copyright (c) 2014-2015 Sven Karlsson 4 * All rights reserved 5 * 6 * The license below extends only to copyright in the software and shall 7 * not be construed as granting a license to any other intellectual 8 * property including but not limited to intellectual property relating 9 * to a hardware implementation of the functionality of the software 10 * licensed hereunder. You may use the software subject to the license 11 * terms below provided that you ensure that this notice is replicated 12 * unmodified and in its entirety in all distributions of the software, 13 * modified or unmodified, in source code or in binary form. 14 * 15 * Copyright (c) 2016 RISC-V Foundation 16 * Copyright (c) 2016 The University of Virginia 17 * All rights reserved. 18 * 19 * Redistribution and use in source and binary forms, with or without 20 * modification, are permitted provided that the following conditions are 21 * met: redistributions of source code must retain the above copyright 22 * notice, this list of conditions and the following disclaimer; 23 * redistributions in binary form must reproduce the above copyright 24 * notice, this list of conditions and the following disclaimer in the 25 * documentation and/or other materials provided with the distribution; 26 * neither the name of the copyright holders nor the names of its 27 * contributors may be used to endorse or promote products derived from 28 * this software without specific prior written permission. 29 * 30 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 31 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 32 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 33 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 34 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 35 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 36 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 37 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 38 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 39 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 40 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 41 * 42 * Authors: Andreas Hansson 43 * Sven Karlsson 44 * Alec Roelke 45 */ 46 47#ifndef __ARCH_RISCV_REGISTERS_HH__ 48#define __ARCH_RISCV_REGISTERS_HH__ 49 50#include <map> 51#include <string> 52 53#include "arch/riscv/generated/max_inst_regs.hh" 54#include "base/types.hh" 55#include "sim/system.hh" 56 57namespace RiscvISA { 58 59using RiscvISAInst::MaxInstSrcRegs; 60using RiscvISAInst::MaxInstDestRegs; 61const int MaxMiscDestRegs = 1; 62 63typedef uint_fast16_t RegIndex; 64typedef uint64_t IntReg; 65typedef uint64_t FloatRegBits; 66typedef double FloatReg; 67typedef uint8_t CCReg; // Not applicable to Riscv 68typedef uint64_t MiscReg; 69 70const int NumIntArchRegs = 32;
| 1/* 2 * Copyright (c) 2013 ARM Limited 3 * Copyright (c) 2014-2015 Sven Karlsson 4 * All rights reserved 5 * 6 * The license below extends only to copyright in the software and shall 7 * not be construed as granting a license to any other intellectual 8 * property including but not limited to intellectual property relating 9 * to a hardware implementation of the functionality of the software 10 * licensed hereunder. You may use the software subject to the license 11 * terms below provided that you ensure that this notice is replicated 12 * unmodified and in its entirety in all distributions of the software, 13 * modified or unmodified, in source code or in binary form. 14 * 15 * Copyright (c) 2016 RISC-V Foundation 16 * Copyright (c) 2016 The University of Virginia 17 * All rights reserved. 18 * 19 * Redistribution and use in source and binary forms, with or without 20 * modification, are permitted provided that the following conditions are 21 * met: redistributions of source code must retain the above copyright 22 * notice, this list of conditions and the following disclaimer; 23 * redistributions in binary form must reproduce the above copyright 24 * notice, this list of conditions and the following disclaimer in the 25 * documentation and/or other materials provided with the distribution; 26 * neither the name of the copyright holders nor the names of its 27 * contributors may be used to endorse or promote products derived from 28 * this software without specific prior written permission. 29 * 30 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 31 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 32 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 33 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 34 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 35 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 36 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 37 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 38 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 39 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 40 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 41 * 42 * Authors: Andreas Hansson 43 * Sven Karlsson 44 * Alec Roelke 45 */ 46 47#ifndef __ARCH_RISCV_REGISTERS_HH__ 48#define __ARCH_RISCV_REGISTERS_HH__ 49 50#include <map> 51#include <string> 52 53#include "arch/riscv/generated/max_inst_regs.hh" 54#include "base/types.hh" 55#include "sim/system.hh" 56 57namespace RiscvISA { 58 59using RiscvISAInst::MaxInstSrcRegs; 60using RiscvISAInst::MaxInstDestRegs; 61const int MaxMiscDestRegs = 1; 62 63typedef uint_fast16_t RegIndex; 64typedef uint64_t IntReg; 65typedef uint64_t FloatRegBits; 66typedef double FloatReg; 67typedef uint8_t CCReg; // Not applicable to Riscv 68typedef uint64_t MiscReg; 69 70const int NumIntArchRegs = 32;
|
93 94const char* const RegisterNames[] = {"zero", "ra", "sp", "gp", 95 "tp", "t0", "t1", "t2", 96 "s0", "s1", "a0", "a1", 97 "a2", "a3", "a4", "a5", 98 "a6", "a7", "s2", "s3", 99 "s4", "s5", "s6", "s7", 100 "s8", "s9", "s10", "s11", 101 "t3", "t4", "t5", "t6"}; 102 103const int SyscallNumReg = ArgumentRegs[7]; 104const int SyscallArgumentRegs[] = {ArgumentRegs[0], ArgumentRegs[1], 105 ArgumentRegs[2], ArgumentRegs[3]}; 106const int SyscallPseudoReturnReg = ReturnValueRegs[0]; 107 108enum MiscRegIndex { 109 MISCREG_FFLAGS = 0x001, 110 MISCREG_FRM = 0x002, 111 MISCREG_FCSR = 0x003, 112 MISCREG_CYCLE = 0xC00, 113 MISCREG_TIME = 0xC01, 114 MISCREG_INSTRET = 0xC02, 115 MISCREG_CYCLEH = 0xC80, 116 MISCREG_TIMEH = 0xC81, 117 MISCREG_INSTRETH = 0xC82, 118 119 MISCREG_SSTATUS = 0x100, 120 MISCREG_STVEC = 0x101, 121 MISCREG_SIE = 0x104, 122 MISCREG_STIMECMP = 0x121, 123 MISCREG_STIME = 0xD01, 124 MISCREG_STIMEH = 0xD81, 125 MISCREG_SSCRATCH = 0x140, 126 MISCREG_SEPC = 0x141, 127 MISCREG_SCAUSE = 0xD42, 128 MISCREG_SBADADDR = 0xD43, 129 MISCREG_SIP = 0x144, 130 MISCREG_SPTBR = 0x180, 131 MISCREG_SASID = 0x181, 132 MISCREG_CYCLEW = 0x900, 133 MISCREG_TIMEW = 0x901, 134 MISCREG_INSTRETW = 0x902, 135 MISCREG_CYCLEHW = 0x980, 136 MISCREG_TIMEHW = 0x981, 137 MISCREG_INSTRETHW = 0x982, 138 139 MISCREG_HSTATUS = 0x200, 140 MISCREG_HTVEC = 0x201, 141 MISCREG_HTDELEG = 0x202, 142 MISCREG_HTIMECMP = 0x221, 143 MISCREG_HTIME = 0xE01, 144 MISCREG_HTIMEH = 0xE81, 145 MISCREG_HSCRATCH = 0x240, 146 MISCREG_HEPC = 0x241, 147 MISCREG_HCAUSE = 0x242, 148 MISCREG_HBADADDR = 0x243, 149 MISCREG_STIMEW = 0xA01, 150 MISCREG_STIMEHW = 0xA81, 151 152 MISCREG_MCPUID = 0xF00, 153 MISCREG_MIMPID = 0xF01, 154 MISCREG_MHARTID = 0xF10, 155 MISCREG_MSTATUS = 0x300, 156 MISCREG_MTVEC = 0x301, 157 MISCREG_MTDELEG = 0x302, 158 MISCREG_MIE = 0x304, 159 MISCREG_MTIMECMP = 0x321, 160 MISCREG_MTIME = 0x701, 161 MISCREG_MTIMEH = 0x741, 162 MISCREG_MSCRATCH = 0x340, 163 MISCREG_MEPC = 0x341, 164 MISCREG_MCAUSE = 0x342, 165 MISCREG_MBADADDR = 0x343, 166 MISCREG_MIP = 0x344, 167 MISCREG_MBASE = 0x380, 168 MISCREG_MBOUND = 0x381, 169 MISCREG_MIBASE = 0x382, 170 MISCREG_MIBOUND = 0x383, 171 MISCREG_MDBASE = 0x384, 172 MISCREG_MDBOUND = 0x385, 173 MISCREG_HTIMEW = 0xB01, 174 MISCREG_HTIMEHW = 0xB81, 175 MISCREG_MTOHOST = 0x780, 176 MISCREG_MFROMHOST = 0x781 177}; 178 179} 180 181#endif // __ARCH_RISCV_REGISTERS_HH__
| 94 95const char* const RegisterNames[] = {"zero", "ra", "sp", "gp", 96 "tp", "t0", "t1", "t2", 97 "s0", "s1", "a0", "a1", 98 "a2", "a3", "a4", "a5", 99 "a6", "a7", "s2", "s3", 100 "s4", "s5", "s6", "s7", 101 "s8", "s9", "s10", "s11", 102 "t3", "t4", "t5", "t6"}; 103 104const int SyscallNumReg = ArgumentRegs[7]; 105const int SyscallArgumentRegs[] = {ArgumentRegs[0], ArgumentRegs[1], 106 ArgumentRegs[2], ArgumentRegs[3]}; 107const int SyscallPseudoReturnReg = ReturnValueRegs[0]; 108 109enum MiscRegIndex { 110 MISCREG_FFLAGS = 0x001, 111 MISCREG_FRM = 0x002, 112 MISCREG_FCSR = 0x003, 113 MISCREG_CYCLE = 0xC00, 114 MISCREG_TIME = 0xC01, 115 MISCREG_INSTRET = 0xC02, 116 MISCREG_CYCLEH = 0xC80, 117 MISCREG_TIMEH = 0xC81, 118 MISCREG_INSTRETH = 0xC82, 119 120 MISCREG_SSTATUS = 0x100, 121 MISCREG_STVEC = 0x101, 122 MISCREG_SIE = 0x104, 123 MISCREG_STIMECMP = 0x121, 124 MISCREG_STIME = 0xD01, 125 MISCREG_STIMEH = 0xD81, 126 MISCREG_SSCRATCH = 0x140, 127 MISCREG_SEPC = 0x141, 128 MISCREG_SCAUSE = 0xD42, 129 MISCREG_SBADADDR = 0xD43, 130 MISCREG_SIP = 0x144, 131 MISCREG_SPTBR = 0x180, 132 MISCREG_SASID = 0x181, 133 MISCREG_CYCLEW = 0x900, 134 MISCREG_TIMEW = 0x901, 135 MISCREG_INSTRETW = 0x902, 136 MISCREG_CYCLEHW = 0x980, 137 MISCREG_TIMEHW = 0x981, 138 MISCREG_INSTRETHW = 0x982, 139 140 MISCREG_HSTATUS = 0x200, 141 MISCREG_HTVEC = 0x201, 142 MISCREG_HTDELEG = 0x202, 143 MISCREG_HTIMECMP = 0x221, 144 MISCREG_HTIME = 0xE01, 145 MISCREG_HTIMEH = 0xE81, 146 MISCREG_HSCRATCH = 0x240, 147 MISCREG_HEPC = 0x241, 148 MISCREG_HCAUSE = 0x242, 149 MISCREG_HBADADDR = 0x243, 150 MISCREG_STIMEW = 0xA01, 151 MISCREG_STIMEHW = 0xA81, 152 153 MISCREG_MCPUID = 0xF00, 154 MISCREG_MIMPID = 0xF01, 155 MISCREG_MHARTID = 0xF10, 156 MISCREG_MSTATUS = 0x300, 157 MISCREG_MTVEC = 0x301, 158 MISCREG_MTDELEG = 0x302, 159 MISCREG_MIE = 0x304, 160 MISCREG_MTIMECMP = 0x321, 161 MISCREG_MTIME = 0x701, 162 MISCREG_MTIMEH = 0x741, 163 MISCREG_MSCRATCH = 0x340, 164 MISCREG_MEPC = 0x341, 165 MISCREG_MCAUSE = 0x342, 166 MISCREG_MBADADDR = 0x343, 167 MISCREG_MIP = 0x344, 168 MISCREG_MBASE = 0x380, 169 MISCREG_MBOUND = 0x381, 170 MISCREG_MIBASE = 0x382, 171 MISCREG_MIBOUND = 0x383, 172 MISCREG_MDBASE = 0x384, 173 MISCREG_MDBOUND = 0x385, 174 MISCREG_HTIMEW = 0xB01, 175 MISCREG_HTIMEHW = 0xB81, 176 MISCREG_MTOHOST = 0x780, 177 MISCREG_MFROMHOST = 0x781 178}; 179 180} 181 182#endif // __ARCH_RISCV_REGISTERS_HH__
|