1/*
2 * Copyright (c) 2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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33#define __RISCV_PROCESS_HH__
34
35#include <string>
36#include <vector>
37
38#include "mem/page_table.hh"
39#include "sim/process.hh"
40
41class LiveProcess;
41class ObjectFile;
42class System;
43
45class RiscvLiveProcess : public LiveProcess
44class RiscvProcess : public Process
45{
46 protected:
48 RiscvLiveProcess(LiveProcessParams * params, ObjectFile *objFile);
47 RiscvProcess(ProcessParams * params, ObjectFile *objFile);
48
49 void initState();
50
51 template<class IntType>
52 void argsInit(int pageSize);
53
54 public:
55 RiscvISA::IntReg getSyscallArg(ThreadContext *tc, int &i);
56 /// Explicitly import the otherwise hidden getSyscallArg
58 using LiveProcess::getSyscallArg;
57 using Process::getSyscallArg;
58 void setSyscallArg(ThreadContext *tc, int i, RiscvISA::IntReg val);
59 void setSyscallReturn(ThreadContext *tc, SyscallReturn return_value);
60};
61
62/* No architectural page table defined for this ISA */
63typedef NoArchPageTable ArchPageTable;
64
65
66#endif // __RISCV_PROCESS_HH__