1/*
2 * Copyright (c) 2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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33#define __RISCV_PROCESS_HH__
34
35#include <string>
36#include <vector>
37
38#include "mem/page_table.hh"
39#include "sim/process.hh"
40
41class LiveProcess;
42class ObjectFile;
43class System;
44
45class RiscvLiveProcess : public LiveProcess
46{
47 protected:
48 RiscvLiveProcess(LiveProcessParams * params, ObjectFile *objFile);
49
50 void initState();
51
52 template<class IntType>
53 void argsInit(int pageSize);
54
55 public:
56 RiscvISA::IntReg getSyscallArg(ThreadContext *tc, int &i);
57 /// Explicitly import the otherwise hidden getSyscallArg
58 using LiveProcess::getSyscallArg;
59 void setSyscallArg(ThreadContext *tc, int i, RiscvISA::IntReg val);
60 void setSyscallReturn(ThreadContext *tc, SyscallReturn return_value);
61};
62
63/* No architectural page table defined for this ISA */
64typedef NoArchPageTable ArchPageTable;
65
66
67#endif // __RISCV_PROCESS_HH__