process.cc (11806:ada5603bdb1c) | process.cc (11851:824055fe6b30) |
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1/* 2 * Copyright (c) 2004-2005 The Regents of The University of Michigan 3 * Copyright (c) 2016 The University of Virginia 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions are 8 * met: redistributions of source code must retain the above copyright --- 36 unchanged lines hidden (view full) --- 45#include "sim/process.hh" 46#include "sim/process_impl.hh" 47#include "sim/syscall_return.hh" 48#include "sim/system.hh" 49 50using namespace std; 51using namespace RiscvISA; 52 | 1/* 2 * Copyright (c) 2004-2005 The Regents of The University of Michigan 3 * Copyright (c) 2016 The University of Virginia 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions are 8 * met: redistributions of source code must retain the above copyright --- 36 unchanged lines hidden (view full) --- 45#include "sim/process.hh" 46#include "sim/process_impl.hh" 47#include "sim/syscall_return.hh" 48#include "sim/system.hh" 49 50using namespace std; 51using namespace RiscvISA; 52 |
53RiscvLiveProcess::RiscvLiveProcess(LiveProcessParams * params, 54 ObjectFile *objFile) : LiveProcess(params, objFile) | 53RiscvProcess::RiscvProcess(ProcessParams * params, 54 ObjectFile *objFile) : Process(params, objFile) |
55{ 56 // Set up stack. On RISC-V, stack starts at the top of kuseg 57 // user address space. RISC-V stack grows down from here 58 stack_base = 0x7FFFFFFF; 59 60 // Set pointer for next thread stack. Reserve 8M for main stack. 61 next_thread_stack_base = stack_base - (8 * 1024 * 1024); 62 63 // Set up break point (Top of Heap) 64 brk_point = objFile->bssBase() + objFile->bssSize(); 65 66 // Set up region for mmaps. Start it 1GB above the top of the heap. 67 mmap_end = brk_point + 0x40000000L; 68} 69 70void | 55{ 56 // Set up stack. On RISC-V, stack starts at the top of kuseg 57 // user address space. RISC-V stack grows down from here 58 stack_base = 0x7FFFFFFF; 59 60 // Set pointer for next thread stack. Reserve 8M for main stack. 61 next_thread_stack_base = stack_base - (8 * 1024 * 1024); 62 63 // Set up break point (Top of Heap) 64 brk_point = objFile->bssBase() + objFile->bssSize(); 65 66 // Set up region for mmaps. Start it 1GB above the top of the heap. 67 mmap_end = brk_point + 0x40000000L; 68} 69 70void |
71RiscvLiveProcess::initState() | 71RiscvProcess::initState() |
72{ | 72{ |
73 LiveProcess::initState(); | 73 Process::initState(); |
74 75 argsInit<uint64_t>(PageBytes); 76} 77 78template<class IntType> void | 74 75 argsInit<uint64_t>(PageBytes); 76} 77 78template<class IntType> void |
79RiscvLiveProcess::argsInit(int pageSize) | 79RiscvProcess::argsInit(int pageSize) |
80{ 81 updateBias(); 82 83 // load object file into target memory 84 objFile->loadSections(initVirtMem); 85 86 typedef AuxVector<IntType> auxv_t; 87 vector<auxv_t> auxv; --- 122 unchanged lines hidden (view full) --- 210 } 211 212 ThreadContext *tc = system->getThreadContext(contextIds[0]); 213 tc->setIntReg(StackPointerReg, stack_min); 214 tc->pcState(getStartPC()); 215} 216 217RiscvISA::IntReg | 80{ 81 updateBias(); 82 83 // load object file into target memory 84 objFile->loadSections(initVirtMem); 85 86 typedef AuxVector<IntType> auxv_t; 87 vector<auxv_t> auxv; --- 122 unchanged lines hidden (view full) --- 210 } 211 212 ThreadContext *tc = system->getThreadContext(contextIds[0]); 213 tc->setIntReg(StackPointerReg, stack_min); 214 tc->pcState(getStartPC()); 215} 216 217RiscvISA::IntReg |
218RiscvLiveProcess::getSyscallArg(ThreadContext *tc, int &i) | 218RiscvProcess::getSyscallArg(ThreadContext *tc, int &i) |
219{ 220 // RISC-V only has four system call argument registers by convention, so 221 // if a larger index is requested return 0 222 RiscvISA::IntReg retval = 0; 223 if (i < 4) 224 retval = tc->readIntReg(SyscallArgumentRegs[i]); 225 i++; 226 return retval; 227} 228 229void | 219{ 220 // RISC-V only has four system call argument registers by convention, so 221 // if a larger index is requested return 0 222 RiscvISA::IntReg retval = 0; 223 if (i < 4) 224 retval = tc->readIntReg(SyscallArgumentRegs[i]); 225 i++; 226 return retval; 227} 228 229void |
230RiscvLiveProcess::setSyscallArg(ThreadContext *tc, int i, RiscvISA::IntReg val) | 230RiscvProcess::setSyscallArg(ThreadContext *tc, int i, RiscvISA::IntReg val) |
231{ 232 tc->setIntReg(SyscallArgumentRegs[i], val); 233} 234 235void | 231{ 232 tc->setIntReg(SyscallArgumentRegs[i], val); 233} 234 235void |
236RiscvLiveProcess::setSyscallReturn(ThreadContext *tc, SyscallReturn sysret) | 236RiscvProcess::setSyscallReturn(ThreadContext *tc, SyscallReturn sysret) |
237{ 238 if (sysret.successful()) { 239 // no error 240 tc->setIntReg(SyscallPseudoReturnReg, sysret.returnValue()); 241 } else { 242 // got an error, return details 243 tc->setIntReg(SyscallPseudoReturnReg, sysret.errnoValue()); 244 } 245} | 237{ 238 if (sysret.successful()) { 239 // no error 240 tc->setIntReg(SyscallPseudoReturnReg, sysret.returnValue()); 241 } else { 242 // got an error, return details 243 tc->setIntReg(SyscallPseudoReturnReg, sysret.errnoValue()); 244 } 245} |