process.cc (11905:4a771f8756ad) | process.cc (11964:0b67d2ce9801) |
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1/* 2 * Copyright (c) 2004-2005 The Regents of The University of Michigan 3 * Copyright (c) 2016 The University of Virginia 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions are 8 * met: redistributions of source code must retain the above copyright --- 19 unchanged lines hidden (view full) --- 28 * 29 * Authors: Gabe Black 30 * Ali Saidi 31 * Korey Sewell 32 * Alec Roelke 33 */ 34#include "arch/riscv/process.hh" 35 | 1/* 2 * Copyright (c) 2004-2005 The Regents of The University of Michigan 3 * Copyright (c) 2016 The University of Virginia 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions are 8 * met: redistributions of source code must retain the above copyright --- 19 unchanged lines hidden (view full) --- 28 * 29 * Authors: Gabe Black 30 * Ali Saidi 31 * Korey Sewell 32 * Alec Roelke 33 */ 34#include "arch/riscv/process.hh" 35 |
36#include <algorithm> 37#include <cstddef> 38#include <iostream> 39#include <map> 40#include <string> |
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36#include <vector> 37 38#include "arch/riscv/isa_traits.hh" 39#include "base/loader/elf_object.hh" 40#include "base/loader/object_file.hh" 41#include "base/misc.hh" 42#include "cpu/thread_context.hh" | 41#include <vector> 42 43#include "arch/riscv/isa_traits.hh" 44#include "base/loader/elf_object.hh" 45#include "base/loader/object_file.hh" 46#include "base/misc.hh" 47#include "cpu/thread_context.hh" |
43#include "debug/Loader.hh" | 48#include "debug/Stack.hh" |
44#include "mem/page_table.hh" | 49#include "mem/page_table.hh" |
50#include "params/Process.hh" |
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45#include "sim/aux_vector.hh" 46#include "sim/process.hh" 47#include "sim/process_impl.hh" 48#include "sim/syscall_return.hh" 49#include "sim/system.hh" 50 51using namespace std; 52using namespace RiscvISA; 53 54RiscvProcess::RiscvProcess(ProcessParams * params, 55 ObjectFile *objFile) : Process(params, objFile) 56{ | 51#include "sim/aux_vector.hh" 52#include "sim/process.hh" 53#include "sim/process_impl.hh" 54#include "sim/syscall_return.hh" 55#include "sim/system.hh" 56 57using namespace std; 58using namespace RiscvISA; 59 60RiscvProcess::RiscvProcess(ProcessParams * params, 61 ObjectFile *objFile) : Process(params, objFile) 62{ |
57 // Set up stack. On RISC-V, stack starts at the top of kuseg 58 // user address space. RISC-V stack grows down from here 59 Addr stack_base = 0x7FFFFFFF; 60 61 Addr max_stack_size = 8 * 1024 * 1024; 62 63 // Set pointer for next thread stack. Reserve 8M for main stack. 64 Addr next_thread_stack_base = stack_base - max_stack_size; 65 66 // Set up break point (Top of Heap) 67 Addr brk_point = objFile->bssBase() + objFile->bssSize(); 68 69 // Set up region for mmaps. Start it 1GB above the top of the heap. 70 Addr mmap_end = brk_point + 0x40000000L; 71 | 63 const Addr mem_base = 0x80000000; 64 const Addr stack_base = mem_base; 65 const Addr max_stack_size = PageBytes * 64; 66 const Addr next_thread_stack_base = stack_base - max_stack_size; 67 const Addr brk_point = roundUp(objFile->bssBase() + objFile->bssSize(), 68 PageBytes); 69 const Addr mmap_end = mem_base; |
72 memState = make_shared<MemState>(brk_point, stack_base, max_stack_size, | 70 memState = make_shared<MemState>(brk_point, stack_base, max_stack_size, |
73 next_thread_stack_base, mmap_end); | 71 next_thread_stack_base, mmap_end); |
74} 75 76void 77RiscvProcess::initState() 78{ 79 Process::initState(); 80 81 argsInit<uint64_t>(PageBytes); 82} 83 84template<class IntType> void 85RiscvProcess::argsInit(int pageSize) 86{ 87 updateBias(); | 72} 73 74void 75RiscvProcess::initState() 76{ 77 Process::initState(); 78 79 argsInit<uint64_t>(PageBytes); 80} 81 82template<class IntType> void 83RiscvProcess::argsInit(int pageSize) 84{ 85 updateBias(); |
88 89 // load object file into target memory | |
90 objFile->loadSections(initVirtMem); | 86 objFile->loadSections(initVirtMem); |
87 ElfObject* elfObject = dynamic_cast<ElfObject*>(objFile); 88 memState->setStackMin(memState->getStackBase()); |
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91 | 89 |
92 typedef AuxVector<IntType> auxv_t; 93 vector<auxv_t> auxv; 94 ElfObject * elfObject = dynamic_cast<ElfObject *>(objFile); 95 if (elfObject) { 96 // Set the system page size 97 auxv.push_back(auxv_t(M5_AT_PAGESZ, RiscvISA::PageBytes)); 98 // Set the frequency at which time() increments 99 auxv.push_back(auxv_t(M5_AT_CLKTCK, 100)); 100 // For statically linked executables, this is the virtual 101 // address of the program header tables if they appear in the 102 // executable image. 103 auxv.push_back(auxv_t(M5_AT_PHDR, elfObject->programHeaderTable())); 104 DPRINTF(Loader, "auxv at PHDR %08p\n", 105 elfObject->programHeaderTable()); 106 // This is the size of a program header entry from the elf file. 107 auxv.push_back(auxv_t(M5_AT_PHENT, elfObject->programHeaderSize())); 108 // This is the number of program headers from the original elf file. 109 auxv.push_back(auxv_t(M5_AT_PHNUM, elfObject->programHeaderCount())); 110 auxv.push_back(auxv_t(M5_AT_BASE, getBias())); 111 //The entry point to the program 112 auxv.push_back(auxv_t(M5_AT_ENTRY, objFile->entryPoint())); 113 //Different user and group IDs 114 auxv.push_back(auxv_t(M5_AT_UID, uid())); 115 auxv.push_back(auxv_t(M5_AT_EUID, euid())); 116 auxv.push_back(auxv_t(M5_AT_GID, gid())); 117 auxv.push_back(auxv_t(M5_AT_EGID, egid())); | 90 // Determine stack size and populate auxv 91 Addr stack_top = memState->getStackMin(); 92 for (const string& arg: argv) 93 stack_top -= arg.size() + 1; 94 for (const string& env: envp) 95 stack_top -= env.size() + 1; 96 stack_top &= -sizeof(Addr); 97 98 vector<AuxVector<IntType>> auxv; 99 if (elfObject != nullptr) { 100 auxv.push_back({M5_AT_ENTRY, objFile->entryPoint()}); 101 auxv.push_back({M5_AT_PHNUM, elfObject->programHeaderCount()}); 102 auxv.push_back({M5_AT_PHENT, elfObject->programHeaderSize()}); 103 auxv.push_back({M5_AT_PHDR, elfObject->programHeaderTable()}); 104 auxv.push_back({M5_AT_PAGESZ, PageBytes}); 105 auxv.push_back({M5_AT_SECURE, 0}); 106 auxv.push_back({M5_AT_RANDOM, stack_top}); 107 auxv.push_back({M5_AT_NULL, 0}); |
118 } | 108 } |
109 stack_top -= (1 + argv.size()) * sizeof(Addr) + 110 (1 + envp.size()) * sizeof(Addr) + 111 sizeof(Addr) + 2 * sizeof(IntType) * auxv.size(); 112 stack_top &= -2*sizeof(Addr); 113 memState->setStackSize(memState->getStackBase() - stack_top); 114 allocateMem(roundDown(stack_top, pageSize), 115 roundUp(memState->getStackSize(), pageSize)); |
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119 | 116 |
120 const IntType zero = 0; 121 IntType argc = htog((IntType)argv.size()); 122 int argv_array_size = sizeof(Addr) * argv.size(); 123 int arg_data_size = 0; 124 for (string arg: argv) 125 arg_data_size += arg.size() + 1; 126 int envp_array_size = sizeof(Addr) * envp.size(); 127 int env_data_size = 0; 128 for (string env: envp) 129 env_data_size += env.size() + 1; 130 int auxv_array_size = 2 * sizeof(IntType)*auxv.size(); | 117 // Copy argv to stack 118 vector<Addr> argPointers; 119 for (const string& arg: argv) { 120 memState->setStackMin(memState->getStackMin() - (arg.size() + 1)); 121 initVirtMem.writeString(memState->getStackMin(), arg.c_str()); 122 argPointers.push_back(memState->getStackMin()); 123 if (DTRACE(Stack)) { 124 string wrote; 125 initVirtMem.readString(wrote, argPointers.back()); 126 DPRINTFN("Wrote arg \"%s\" to address %p\n", 127 wrote, (void*)memState->getStackMin()); 128 } 129 } 130 argPointers.push_back(0); |
131 | 131 |
132 Addr stack_size = sizeof(IntType) + argv_array_size + 2 * sizeof(Addr) + 133 sizeof(Addr) + arg_data_size + 2 * sizeof(Addr); 134 if (!envp.empty()) { 135 stack_size += 2 * sizeof(Addr) + envp_array_size + 2 * 136 sizeof(Addr) + env_data_size; | 132 // Copy envp to stack 133 vector<Addr> envPointers; 134 for (const string& env: envp) { 135 memState->setStackMin(memState->getStackMin() - (env.size() + 1)); 136 initVirtMem.writeString(memState->getStackMin(), env.c_str()); 137 envPointers.push_back(memState->getStackMin()); 138 DPRINTF(Stack, "Wrote env \"%s\" to address %p\n", 139 env, (void*)memState->getStackMin()); |
137 } | 140 } |
138 if (!auxv.empty()) 139 stack_size += 2 * sizeof(Addr) + auxv_array_size; | 141 envPointers.push_back(0); |
140 | 142 |
141 memState->setStackSize(stack_size); | 143 // Align stack 144 memState->setStackMin(memState->getStackMin() & -sizeof(Addr)); |
142 | 145 |
143 Addr stack_min = roundDown(memState->getStackBase() - 144 stack_size, pageSize); 145 allocateMem(stack_min, roundUp(memState->getStackSize(), pageSize)); | 146 // Calculate bottom of stack 147 memState->setStackMin(memState->getStackMin() - 148 ((1 + argv.size()) * sizeof(Addr) + 149 (1 + envp.size()) * sizeof(Addr) + 150 sizeof(Addr) + 2 * sizeof(IntType) * auxv.size())); 151 memState->setStackMin(memState->getStackMin() & -2*sizeof(Addr)); 152 Addr sp = memState->getStackMin(); 153 const auto pushOntoStack = 154 [this, &sp](const uint8_t* data, const size_t size) { 155 initVirtMem.writeBlob(sp, data, size); 156 sp += size; 157 }; |
146 | 158 |
147 memState->setStackMin(stack_min); 148 149 Addr argv_array_base = memState->getStackMin() + sizeof(IntType); 150 Addr arg_data_base = argv_array_base + argv_array_size + 2 * sizeof(Addr); 151 Addr envp_array_base = arg_data_base + arg_data_size; 152 if (!envp.empty()) 153 envp_array_base += 2 * sizeof(Addr); 154 Addr env_data_base = envp_array_base + envp_array_size; 155 if (!envp.empty()) 156 env_data_base += 2 * sizeof(Addr); 157 158 vector<Addr> arg_pointers; 159 if (!argv.empty()) { 160 arg_pointers.push_back(arg_data_base); 161 for (int i = 0; i < argv.size() - 1; i++) { 162 arg_pointers.push_back(arg_pointers[i] + argv[i].size() + 1); 163 } | 159 // Push argc and argv pointers onto stack 160 IntType argc = htog((IntType)argv.size()); 161 DPRINTF(Stack, "Wrote argc %d to address %p\n", 162 argv.size(), (void*)sp); 163 pushOntoStack((uint8_t*)&argc, sizeof(IntType)); 164 for (const Addr& argPointer: argPointers) { 165 DPRINTF(Stack, "Wrote argv pointer %p to address %p\n", 166 (void*)argPointer, (void*)sp); 167 pushOntoStack((uint8_t*)&argPointer, sizeof(Addr)); |
164 } 165 | 168 } 169 |
166 vector<Addr> env_pointers; 167 if (!envp.empty()) { 168 env_pointers.push_back(env_data_base); 169 for (int i = 0; i < envp.size() - 1; i++) { 170 env_pointers.push_back(env_pointers[i] + envp[i].size() + 1); 171 } | 170 // Push env pointers onto stack 171 for (const Addr& envPointer: envPointers) { 172 DPRINTF(Stack, "Wrote envp pointer %p to address %p\n", 173 (void*)envPointer, (void*)sp); 174 pushOntoStack((uint8_t*)&envPointer, sizeof(Addr)); |
172 } 173 | 175 } 176 |
174 Addr sp = memState->getStackMin(); 175 initVirtMem.writeBlob(sp, (uint8_t *)&argc, sizeof(IntType)); 176 sp += sizeof(IntType); 177 for (Addr arg_pointer: arg_pointers) { 178 initVirtMem.writeBlob(sp, (uint8_t *)&arg_pointer, sizeof(Addr)); 179 sp += sizeof(Addr); | 177 // Push aux vector onto stack 178 std::map<IntType, string> aux_keys = { 179 {M5_AT_ENTRY, "M5_AT_ENTRY"}, 180 {M5_AT_PHNUM, "M5_AT_PHNUM"}, 181 {M5_AT_PHENT, "M5_AT_PHENT"}, 182 {M5_AT_PHDR, "M5_AT_PHDR"}, 183 {M5_AT_PAGESZ, "M5_AT_PAGESZ"}, 184 {M5_AT_SECURE, "M5_AT_SECURE"}, 185 {M5_AT_RANDOM, "M5_AT_RANDOM"}, 186 {M5_AT_NULL, "M5_AT_NULL"} 187 }; 188 for (const AuxVector<IntType>& aux: auxv) { 189 DPRINTF(Stack, "Wrote aux key %s to address %p\n", 190 aux_keys[aux.a_type], (void*)sp); 191 pushOntoStack((uint8_t*)&aux.a_type, sizeof(IntType)); 192 DPRINTF(Stack, "Wrote aux value %x to address %p\n", 193 aux.a_val, (void*)sp); 194 pushOntoStack((uint8_t*)&aux.a_val, sizeof(IntType)); |
180 } | 195 } |
181 for (int i = 0; i < 2; i++) { 182 initVirtMem.writeBlob(sp, (uint8_t *)&zero, sizeof(Addr)); 183 sp += sizeof(Addr); 184 } 185 for (int i = 0; i < argv.size(); i++) { 186 initVirtMem.writeString(sp, argv[i].c_str()); 187 sp += argv[i].size() + 1; 188 } 189 if (!envp.empty()) { 190 for (int i = 0; i < 2; i++) { 191 initVirtMem.writeBlob(sp, (uint8_t *)&zero, sizeof(Addr)); 192 sp += sizeof(Addr); 193 } 194 } 195 for (Addr env_pointer: env_pointers) 196 initVirtMem.writeBlob(sp, (uint8_t *)&env_pointer, sizeof(Addr)); 197 if (!envp.empty()) { 198 for (int i = 0; i < 2; i++) { 199 initVirtMem.writeBlob(sp, (uint8_t *)&zero, sizeof(Addr)); 200 sp += sizeof(Addr); 201 } 202 } 203 for (int i = 0; i < envp.size(); i++) { 204 initVirtMem.writeString(sp, envp[i].c_str()); 205 sp += envp[i].size() + 1; 206 } 207 if (!auxv.empty()) { 208 for (int i = 0; i < 2; i++) { 209 initVirtMem.writeBlob(sp, (uint8_t *)&zero, sizeof(Addr)); 210 sp += sizeof(Addr); 211 } 212 } 213 for (auxv_t aux: auxv) { 214 initVirtMem.writeBlob(sp, (uint8_t *)&aux.a_type, sizeof(IntType)); 215 initVirtMem.writeBlob(sp + sizeof(IntType), (uint8_t *)&aux.a_val, 216 sizeof(IntType)); 217 sp += 2 * sizeof(IntType); 218 } 219 for (int i = 0; i < 2; i++) { 220 initVirtMem.writeBlob(sp, (uint8_t *)&zero, sizeof(Addr)); 221 sp += sizeof(Addr); 222 } | |
223 224 ThreadContext *tc = system->getThreadContext(contextIds[0]); 225 tc->setIntReg(StackPointerReg, memState->getStackMin()); 226 tc->pcState(getStartPC()); | 196 197 ThreadContext *tc = system->getThreadContext(contextIds[0]); 198 tc->setIntReg(StackPointerReg, memState->getStackMin()); 199 tc->pcState(getStartPC()); |
200 201 memState->setStackMin(roundDown(memState->getStackMin(), pageSize)); |
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227} 228 229RiscvISA::IntReg 230RiscvProcess::getSyscallArg(ThreadContext *tc, int &i) 231{ 232 // RISC-V only has four system call argument registers by convention, so 233 // if a larger index is requested return 0 234 RiscvISA::IntReg retval = 0; --- 23 unchanged lines hidden --- | 202} 203 204RiscvISA::IntReg 205RiscvProcess::getSyscallArg(ThreadContext *tc, int &i) 206{ 207 // RISC-V only has four system call argument registers by convention, so 208 // if a larger index is requested return 0 209 RiscvISA::IntReg retval = 0; --- 23 unchanged lines hidden --- |