1/*
2 * Copyright (c) 2004-2005 The Regents of The University of Michigan
3 * Copyright (c) 2016 The University of Virginia
4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are
8 * met: redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer;
10 * redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution;
13 * neither the name of the copyright holders nor the names of its
14 * contributors may be used to endorse or promote products derived from
15 * this software without specific prior written permission.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
18 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
19 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
20 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
21 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
22 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
23 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
24 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
25 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
26 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
27 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28 *
29 * Authors: Gabe Black
30 * Ali Saidi
31 * Korey Sewell
32 * Alec Roelke
33 */
34#include "arch/riscv/process.hh"
35
36#include <algorithm>
37#include <cstddef>
38#include <iostream>
39#include <iterator>
40#include <map>
41#include <string>
42#include <vector>
43
44#include "arch/riscv/isa.hh"
45#include "arch/riscv/isa_traits.hh"
46#include "arch/riscv/registers.hh"
47#include "base/loader/elf_object.hh"
48#include "base/loader/object_file.hh"
49#include "base/logging.hh"
50#include "base/random.hh"
51#include "cpu/thread_context.hh"
52#include "debug/Stack.hh"
53#include "mem/page_table.hh"
54#include "params/Process.hh"
55#include "sim/aux_vector.hh"
56#include "sim/process.hh"
57#include "sim/process_impl.hh"
58#include "sim/syscall_return.hh"
59#include "sim/system.hh"
60
61using namespace std;
62using namespace RiscvISA;
63
64RiscvProcess::RiscvProcess(ProcessParams *params, ObjectFile *objFile) :
65 Process(params,
66 new EmulationPageTable(params->name, params->pid, PageBytes),
67 objFile)
68{
69 fatal_if(params->useArchPT, "Arch page tables not implemented.");
70}
71
72RiscvProcess64::RiscvProcess64(ProcessParams *params, ObjectFile *objFile) :
73 RiscvProcess(params, objFile)
74{
75 const Addr stack_base = 0x7FFFFFFFFFFFFFFFL;
76 const Addr max_stack_size = 8 * 1024 * 1024;
77 const Addr next_thread_stack_base = stack_base - max_stack_size;
78 const Addr brk_point = roundUp(objFile->bssBase() + objFile->bssSize(),
79 PageBytes);
80 const Addr mmap_end = 0x4000000000000000L;
81 memState = make_shared<MemState>(brk_point, stack_base, max_stack_size,
82 next_thread_stack_base, mmap_end);
83}
84
85RiscvProcess32::RiscvProcess32(ProcessParams *params, ObjectFile *objFile) :
86 RiscvProcess(params, objFile)
87{
88 const Addr stack_base = 0x7FFFFFFF;
89 const Addr max_stack_size = 8 * 1024 * 1024;
90 const Addr next_thread_stack_base = stack_base - max_stack_size;
91 const Addr brk_point = roundUp(objFile->bssBase() + objFile->bssSize(),
92 PageBytes);
93 const Addr mmap_end = 0x40000000L;
94 memState = make_shared<MemState>(brk_point, stack_base, max_stack_size,
95 next_thread_stack_base, mmap_end);
96}
97
98void
99RiscvProcess64::initState()
100{
101 Process::initState();
102
103 argsInit<uint64_t>(PageBytes);
104 for (ContextID ctx: contextIds)
105 system->getThreadContext(ctx)->setMiscRegNoEffect(MISCREG_PRV, PRV_U);
106}
107
108void
109RiscvProcess32::initState()
110{
111 Process::initState();
112
113 argsInit<uint32_t>(PageBytes);
114 for (ContextID ctx: contextIds) {
115 system->getThreadContext(ctx)->setMiscRegNoEffect(MISCREG_PRV, PRV_U);
116 PCState pc = system->getThreadContext(ctx)->pcState();
117 pc.rv32(true);
118 system->getThreadContext(ctx)->pcState(pc);
119 }
120}
121
122template<class IntType> void
123RiscvProcess::argsInit(int pageSize)
124{
125 const int RandomBytes = 16;
126 const int addrSize = sizeof(IntType);
127
128 updateBias();
129 objFile->loadSections(initVirtMem);
130 ElfObject* elfObject = dynamic_cast<ElfObject*>(objFile);
131 memState->setStackMin(memState->getStackBase());
132
133 // Determine stack size and populate auxv
134 Addr stack_top = memState->getStackMin();
135 stack_top -= RandomBytes;
136 for (const string& arg: argv)
137 stack_top -= arg.size() + 1;
138 for (const string& env: envp)
139 stack_top -= env.size() + 1;
140 stack_top &= -addrSize;
141
142 typedef AuxVector<IntType> auxv_t;
143 vector<auxv_t> auxv;
144 if (elfObject != nullptr) {
145 auxv.push_back(auxv_t(M5_AT_ENTRY, objFile->entryPoint()));
146 auxv.push_back(auxv_t(M5_AT_PHNUM, elfObject->programHeaderCount()));
147 auxv.push_back(auxv_t(M5_AT_PHENT, elfObject->programHeaderSize()));
148 auxv.push_back(auxv_t(M5_AT_PHDR, elfObject->programHeaderTable()));
149 auxv.push_back(auxv_t(M5_AT_PAGESZ, PageBytes));
150 auxv.push_back(auxv_t(M5_AT_SECURE, 0));
151 auxv.push_back(auxv_t(M5_AT_RANDOM, stack_top));
152 auxv.push_back(auxv_t(M5_AT_NULL, 0));
153 }
154 stack_top -= (1 + argv.size()) * addrSize +
155 (1 + envp.size()) * addrSize +
156 addrSize + 2 * sizeof(IntType) * auxv.size();
157 stack_top &= -2*addrSize;
158 memState->setStackSize(memState->getStackBase() - stack_top);
159 allocateMem(roundDown(stack_top, pageSize),
160 roundUp(memState->getStackSize(), pageSize));
161
162 // Copy random bytes (for AT_RANDOM) to stack
163 memState->setStackMin(memState->getStackMin() - RandomBytes);
164 uint8_t at_random[RandomBytes];
165 generate(begin(at_random), end(at_random),
166 [&]{ return random_mt.random(0, 0xFF); });
167 initVirtMem.writeBlob(memState->getStackMin(), at_random, RandomBytes);
168
169 // Copy argv to stack
170 vector<Addr> argPointers;
171 for (const string& arg: argv) {
172 memState->setStackMin(memState->getStackMin() - (arg.size() + 1));
173 initVirtMem.writeString(memState->getStackMin(), arg.c_str());
174 argPointers.push_back(memState->getStackMin());
175 if (DTRACE(Stack)) {
176 string wrote;
177 initVirtMem.readString(wrote, argPointers.back());
178 DPRINTFN("Wrote arg \"%s\" to address %p\n",
179 wrote, (void*)memState->getStackMin());
180 }
181 }
182 argPointers.push_back(0);
183
184 // Copy envp to stack
185 vector<Addr> envPointers;
186 for (const string& env: envp) {
187 memState->setStackMin(memState->getStackMin() - (env.size() + 1));
188 initVirtMem.writeString(memState->getStackMin(), env.c_str());
189 envPointers.push_back(memState->getStackMin());
190 DPRINTF(Stack, "Wrote env \"%s\" to address %p\n",
191 env, (void*)memState->getStackMin());
192 }
193 envPointers.push_back(0);
194
195 // Align stack
196 memState->setStackMin(memState->getStackMin() & -addrSize);
197
198 // Calculate bottom of stack
199 memState->setStackMin(memState->getStackMin() -
200 ((1 + argv.size()) * addrSize +
201 (1 + envp.size()) * addrSize +
202 addrSize + 2 * sizeof(IntType) * auxv.size()));
203 memState->setStackMin(memState->getStackMin() & -2*addrSize);
204 Addr sp = memState->getStackMin();
205 const auto pushOntoStack =
206 [this, &sp](const uint8_t* data, const size_t size) {
207 initVirtMem.writeBlob(sp, data, size);
208 sp += size;
209 };
210
211 // Push argc and argv pointers onto stack
212 IntType argc = htog((IntType)argv.size());
213 DPRINTF(Stack, "Wrote argc %d to address %p\n",
214 argv.size(), (void*)sp);
215 pushOntoStack((uint8_t*)&argc, sizeof(IntType));
216 for (const Addr& argPointer: argPointers) {
217 DPRINTF(Stack, "Wrote argv pointer %p to address %p\n",
218 (void*)argPointer, (void*)sp);
219 pushOntoStack((uint8_t*)&argPointer, addrSize);
220 }
221
222 // Push env pointers onto stack
223 for (const Addr& envPointer: envPointers) {
224 DPRINTF(Stack, "Wrote envp pointer %p to address %p\n",
225 (void*)envPointer, (void*)sp);
226 pushOntoStack((uint8_t*)&envPointer, addrSize);
227 }
228
229 // Push aux vector onto stack
230 std::map<IntType, string> aux_keys = {
231 {M5_AT_ENTRY, "M5_AT_ENTRY"},
232 {M5_AT_PHNUM, "M5_AT_PHNUM"},
233 {M5_AT_PHENT, "M5_AT_PHENT"},
234 {M5_AT_PHDR, "M5_AT_PHDR"},
235 {M5_AT_PAGESZ, "M5_AT_PAGESZ"},
236 {M5_AT_SECURE, "M5_AT_SECURE"},
237 {M5_AT_RANDOM, "M5_AT_RANDOM"},
238 {M5_AT_NULL, "M5_AT_NULL"}
239 };
240 for (const AuxVector<IntType>& aux: auxv) {
241 DPRINTF(Stack, "Wrote aux key %s to address %p\n",
242 aux_keys[aux.getAuxType()], (void*)sp);
243 pushOntoStack((uint8_t*)&aux.getAuxType(), sizeof(IntType));
244 DPRINTF(Stack, "Wrote aux value %x to address %p\n",
245 aux.getAuxVal(), (void*)sp);
246 pushOntoStack((uint8_t*)&aux.getAuxVal(), sizeof(IntType));
247 }
248
249 ThreadContext *tc = system->getThreadContext(contextIds[0]);
250 tc->setIntReg(StackPointerReg, memState->getStackMin());
251 tc->pcState(getStartPC());
252
253 memState->setStackMin(roundDown(memState->getStackMin(), pageSize));
254}
255
256RegVal
257RiscvProcess::getSyscallArg(ThreadContext *tc, int &i)
258{
259 // If a larger index is requested than there are syscall argument
260 // registers, return 0
261 RegVal retval = 0;
262 if (i < SyscallArgumentRegs.size())
263 retval = tc->readIntReg(SyscallArgumentRegs[i]);
264 i++;
265 return retval;
266}
267
268void
269RiscvProcess::setSyscallArg(ThreadContext *tc, int i, RegVal val)
270{
271 tc->setIntReg(SyscallArgumentRegs[i], val);
272}
273
274void
275RiscvProcess::setSyscallReturn(ThreadContext *tc, SyscallReturn sysret)
276{
277 if (sysret.successful()) {
278 // no error
279 tc->setIntReg(SyscallPseudoReturnReg, sysret.returnValue());
280 } else {
281 // got an error, return details
282 tc->setIntReg(SyscallPseudoReturnReg, sysret.encodedValue());
283 }
284}