1/*
2 * Copyright (c) 2004-2005 The Regents of The University of Michigan
3 * Copyright (c) 2016 The University of Virginia
4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are
8 * met: redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer;
10 * redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution;
13 * neither the name of the copyright holders nor the names of its
14 * contributors may be used to endorse or promote products derived from
15 * this software without specific prior written permission.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
18 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
19 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
20 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
21 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
22 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
23 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
24 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
25 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
26 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
27 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28 *
29 * Authors: Gabe Black
30 * Ali Saidi
31 * Korey Sewell
32 * Alec Roelke
33 */
34#include "arch/riscv/process.hh"
35
36#include <vector>
37
38#include "arch/riscv/isa_traits.hh"
39#include "base/loader/elf_object.hh"
40#include "base/loader/object_file.hh"
41#include "base/misc.hh"
42#include "cpu/thread_context.hh"
43#include "debug/Loader.hh"
44#include "mem/page_table.hh"
45#include "sim/aux_vector.hh"
46#include "sim/process.hh"
47#include "sim/process_impl.hh"
48#include "sim/syscall_return.hh"
49#include "sim/system.hh"
50
51using namespace std;
52using namespace RiscvISA;
53
54RiscvProcess::RiscvProcess(ProcessParams * params,
55 ObjectFile *objFile) : Process(params, objFile)
56{
57 // Set up stack. On RISC-V, stack starts at the top of kuseg
58 // user address space. RISC-V stack grows down from here
59 stack_base = 0x7FFFFFFF;
60
61 // Set pointer for next thread stack. Reserve 8M for main stack.
62 next_thread_stack_base = stack_base - (8 * 1024 * 1024);
63
64 // Set up break point (Top of Heap)
65 brk_point = objFile->bssBase() + objFile->bssSize();
66
67 // Set up region for mmaps. Start it 1GB above the top of the heap.
68 mmap_end = brk_point + 0x40000000L;
69}
70
71void
72RiscvProcess::initState()
73{
74 Process::initState();
75
76 argsInit<uint64_t>(PageBytes);
77}
78
79template<class IntType> void
80RiscvProcess::argsInit(int pageSize)
81{
82 updateBias();
83
84 // load object file into target memory
85 objFile->loadSections(initVirtMem);
86
87 typedef AuxVector<IntType> auxv_t;
88 vector<auxv_t> auxv;
89 ElfObject * elfObject = dynamic_cast<ElfObject *>(objFile);
90 if (elfObject) {
91 // Set the system page size
92 auxv.push_back(auxv_t(M5_AT_PAGESZ, RiscvISA::PageBytes));
93 // Set the frequency at which time() increments
94 auxv.push_back(auxv_t(M5_AT_CLKTCK, 100));
95 // For statically linked executables, this is the virtual
96 // address of the program header tables if they appear in the
97 // executable image.
98 auxv.push_back(auxv_t(M5_AT_PHDR, elfObject->programHeaderTable()));
99 DPRINTF(Loader, "auxv at PHDR %08p\n",
100 elfObject->programHeaderTable());
101 // This is the size of a program header entry from the elf file.
102 auxv.push_back(auxv_t(M5_AT_PHENT, elfObject->programHeaderSize()));
103 // This is the number of program headers from the original elf file.
104 auxv.push_back(auxv_t(M5_AT_PHNUM, elfObject->programHeaderCount()));
105 auxv.push_back(auxv_t(M5_AT_BASE, getBias()));
106 //The entry point to the program
107 auxv.push_back(auxv_t(M5_AT_ENTRY, objFile->entryPoint()));
108 //Different user and group IDs
109 auxv.push_back(auxv_t(M5_AT_UID, uid()));
110 auxv.push_back(auxv_t(M5_AT_EUID, euid()));
111 auxv.push_back(auxv_t(M5_AT_GID, gid()));
112 auxv.push_back(auxv_t(M5_AT_EGID, egid()));
113 }
114
115 const IntType zero = 0;
116 IntType argc = htog((IntType)argv.size());
117 int argv_array_size = sizeof(Addr) * argv.size();
118 int arg_data_size = 0;
119 for (string arg: argv)
120 arg_data_size += arg.size() + 1;
121 int envp_array_size = sizeof(Addr) * envp.size();
122 int env_data_size = 0;
123 for (string env: envp)
124 env_data_size += env.size() + 1;
125 int auxv_array_size = 2 * sizeof(IntType)*auxv.size();
126
127 stack_size = sizeof(IntType) + argv_array_size + 2 * sizeof(Addr) +
128 arg_data_size + 2 * sizeof(Addr);
129 if (!envp.empty()) {
130 stack_size += 2 * sizeof(Addr) + envp_array_size + 2 * sizeof(Addr) +
131 env_data_size;
132 }
133 if (!auxv.empty())
134 stack_size += 2 * sizeof(Addr) + auxv_array_size;
135 stack_min = roundDown(stack_base - stack_size, pageSize);
136 allocateMem(stack_min, roundUp(stack_size, pageSize));
137
138 Addr argv_array_base = stack_min + sizeof(IntType);
139 Addr arg_data_base = argv_array_base + argv_array_size + 2 * sizeof(Addr);
140 Addr envp_array_base = arg_data_base + arg_data_size;
141 if (!envp.empty())
142 envp_array_base += 2 * sizeof(Addr);
143 Addr env_data_base = envp_array_base + envp_array_size;
144 if (!envp.empty())
145 env_data_base += 2 * sizeof(Addr);
146
147 vector<Addr> arg_pointers;
148 if (!argv.empty()) {
149 arg_pointers.push_back(arg_data_base);
150 for (int i = 0; i < argv.size() - 1; i++) {
151 arg_pointers.push_back(arg_pointers[i] + argv[i].size() + 1);
152 }
153 }
154
155 vector<Addr> env_pointers;
156 if (!envp.empty()) {
157 env_pointers.push_back(env_data_base);
158 for (int i = 0; i < envp.size() - 1; i++) {
159 env_pointers.push_back(env_pointers[i] + envp[i].size() + 1);
160 }
161 }
162
163 Addr sp = stack_min;
164 initVirtMem.writeBlob(sp, (uint8_t *)&argc, sizeof(IntType));
165 sp += sizeof(IntType);
166 for (Addr arg_pointer: arg_pointers) {
167 initVirtMem.writeBlob(sp, (uint8_t *)&arg_pointer, sizeof(Addr));
168 sp += sizeof(Addr);
169 }
170 for (int i = 0; i < 2; i++) {
171 initVirtMem.writeBlob(sp, (uint8_t *)&zero, sizeof(Addr));
172 sp += sizeof(Addr);
173 }
174 for (int i = 0; i < argv.size(); i++) {
175 initVirtMem.writeString(sp, argv[i].c_str());
176 sp += argv[i].size() + 1;
177 }
178 if (!envp.empty()) {
179 for (int i = 0; i < 2; i++) {
180 initVirtMem.writeBlob(sp, (uint8_t *)&zero, sizeof(Addr));
181 sp += sizeof(Addr);
182 }
183 }
184 for (Addr env_pointer: env_pointers)
185 initVirtMem.writeBlob(sp, (uint8_t *)&env_pointer, sizeof(Addr));
186 if (!envp.empty()) {
187 for (int i = 0; i < 2; i++) {
188 initVirtMem.writeBlob(sp, (uint8_t *)&zero, sizeof(Addr));
189 sp += sizeof(Addr);
190 }
191 }
192 for (int i = 0; i < envp.size(); i++) {
193 initVirtMem.writeString(sp, envp[i].c_str());
194 sp += envp[i].size() + 1;
195 }
196 if (!auxv.empty()) {
197 for (int i = 0; i < 2; i++) {
198 initVirtMem.writeBlob(sp, (uint8_t *)&zero, sizeof(Addr));
199 sp += sizeof(Addr);
200 }
201 }
202 for (auxv_t aux: auxv) {
203 initVirtMem.writeBlob(sp, (uint8_t *)&aux.a_type, sizeof(IntType));
204 initVirtMem.writeBlob(sp + sizeof(IntType), (uint8_t *)&aux.a_val,
205 sizeof(IntType));
206 sp += 2 * sizeof(IntType);
207 }
208 for (int i = 0; i < 2; i++) {
209 initVirtMem.writeBlob(sp, (uint8_t *)&zero, sizeof(Addr));
210 sp += sizeof(Addr);
211 }
212
213 ThreadContext *tc = system->getThreadContext(contextIds[0]);
214 tc->setIntReg(StackPointerReg, stack_min);
215 tc->pcState(getStartPC());
216}
217
218RiscvISA::IntReg
219RiscvProcess::getSyscallArg(ThreadContext *tc, int &i)
220{
221 // RISC-V only has four system call argument registers by convention, so
222 // if a larger index is requested return 0
223 RiscvISA::IntReg retval = 0;
224 if (i < 4)
225 retval = tc->readIntReg(SyscallArgumentRegs[i]);
226 i++;
227 return retval;
228}
229
230void
231RiscvProcess::setSyscallArg(ThreadContext *tc, int i, RiscvISA::IntReg val)
232{
233 tc->setIntReg(SyscallArgumentRegs[i], val);
234}
235
236void
237RiscvProcess::setSyscallReturn(ThreadContext *tc, SyscallReturn sysret)
238{
239 if (sysret.successful()) {
240 // no error
241 tc->setIntReg(SyscallPseudoReturnReg, sysret.returnValue());
242 } else {
243 // got an error, return details
244 tc->setIntReg(SyscallPseudoReturnReg, sysret.errnoValue());
245 }
246}