1/*
2 * Copyright (c) 2004-2005 The Regents of The University of Michigan
3 * Copyright (c) 2016 The University of Virginia
4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are
8 * met: redistributions of source code must retain the above copyright

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55#include "sim/system.hh"
56
57using namespace std;
58using namespace RiscvISA;
59
60RiscvProcess::RiscvProcess(ProcessParams * params,
61 ObjectFile *objFile) : Process(params, objFile)
62{
63 const Addr mem_base = 0x80000000;
64 const Addr stack_base = mem_base;
65 const Addr max_stack_size = PageBytes * 64;
66 const Addr next_thread_stack_base = stack_base - max_stack_size;
67 const Addr brk_point = roundUp(objFile->bssBase() + objFile->bssSize(),
68 PageBytes);
69 const Addr mmap_end = mem_base;
70 memState = make_shared<MemState>(brk_point, stack_base, max_stack_size,
71 next_thread_stack_base, mmap_end);
72}
73
74void
75RiscvProcess::initState()
76{
77 Process::initState();

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