locked_mem.hh (12749:223c83ed9979) locked_mem.hh (13653:079472978bca)
1/*
2 * Copyright (c) 2006 The Regents of The University of Michigan
3 * Copyright (c) 2007-2008 The Florida State University
4 * Copyright (c) 2009 The University of Edinburgh
5 * Copyright (c) 2012 ARM Limited
6 * Copyright (c) 2014-2015 Sven Karlsson
7 * All rights reserved.
8 *

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44 *
45 * Authors: Steve Reinhardt
46 * Alec Roelke
47 */
48#ifndef __ARCH_RISCV_LOCKED_MEM_HH__
49#define __ARCH_RISCV_LOCKED_MEM_HH__
50
51#include <stack>
1/*
2 * Copyright (c) 2006 The Regents of The University of Michigan
3 * Copyright (c) 2007-2008 The Florida State University
4 * Copyright (c) 2009 The University of Edinburgh
5 * Copyright (c) 2012 ARM Limited
6 * Copyright (c) 2014-2015 Sven Karlsson
7 * All rights reserved.
8 *

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44 *
45 * Authors: Steve Reinhardt
46 * Alec Roelke
47 */
48#ifndef __ARCH_RISCV_LOCKED_MEM_HH__
49#define __ARCH_RISCV_LOCKED_MEM_HH__
50
51#include <stack>
52#include <unordered_map>
52
53#include "arch/registers.hh"
54#include "base/logging.hh"
55#include "base/trace.hh"
56#include "debug/LLSC.hh"
57#include "mem/packet.hh"
58#include "mem/request.hh"
59
60/*
61 * ISA-specific helper functions for locked memory accesses.
62 */
63namespace RiscvISA
64{
65
66const int WARN_FAILURE = 10000;
67
68// RISC-V allows multiple locks per hart, but each SC has to unlock the most
69// recent one, so we use a stack here.
53
54#include "arch/registers.hh"
55#include "base/logging.hh"
56#include "base/trace.hh"
57#include "debug/LLSC.hh"
58#include "mem/packet.hh"
59#include "mem/request.hh"
60
61/*
62 * ISA-specific helper functions for locked memory accesses.
63 */
64namespace RiscvISA
65{
66
67const int WARN_FAILURE = 10000;
68
69// RISC-V allows multiple locks per hart, but each SC has to unlock the most
70// recent one, so we use a stack here.
70extern std::stack<Addr> locked_addrs;
71extern std::unordered_map<int, std::stack<Addr>> locked_addrs;
71
72template <class XC> inline void
73handleLockedSnoop(XC *xc, PacketPtr pkt, Addr cacheBlockMask)
74{
72
73template <class XC> inline void
74handleLockedSnoop(XC *xc, PacketPtr pkt, Addr cacheBlockMask)
75{
75 if (locked_addrs.empty())
76 std::stack<Addr>& locked_addr_stack = locked_addrs[xc->contextId()];
77
78 if (locked_addr_stack.empty())
76 return;
77 Addr snoop_addr = pkt->getAddr() & cacheBlockMask;
78 DPRINTF(LLSC, "Locked snoop on address %x.\n", snoop_addr);
79 return;
80 Addr snoop_addr = pkt->getAddr() & cacheBlockMask;
81 DPRINTF(LLSC, "Locked snoop on address %x.\n", snoop_addr);
79 if ((locked_addrs.top() & cacheBlockMask) == snoop_addr)
80 locked_addrs.pop();
82 if ((locked_addr_stack.top() & cacheBlockMask) == snoop_addr)
83 locked_addr_stack.pop();
81}
82
83
84template <class XC> inline void
85handleLockedRead(XC *xc, const RequestPtr &req)
86{
84}
85
86
87template <class XC> inline void
88handleLockedRead(XC *xc, const RequestPtr &req)
89{
87 locked_addrs.push(req->getPaddr() & ~0xF);
90 std::stack<Addr>& locked_addr_stack = locked_addrs[xc->contextId()];
91
92 locked_addr_stack.push(req->getPaddr() & ~0xF);
88 DPRINTF(LLSC, "[cid:%d]: Reserved address %x.\n",
89 req->contextId(), req->getPaddr() & ~0xF);
90}
91
92template <class XC> inline void
93handleLockedSnoopHit(XC *xc)
94{}
95
96template <class XC> inline bool
97handleLockedWrite(XC *xc, const RequestPtr &req, Addr cacheBlockMask)
98{
93 DPRINTF(LLSC, "[cid:%d]: Reserved address %x.\n",
94 req->contextId(), req->getPaddr() & ~0xF);
95}
96
97template <class XC> inline void
98handleLockedSnoopHit(XC *xc)
99{}
100
101template <class XC> inline bool
102handleLockedWrite(XC *xc, const RequestPtr &req, Addr cacheBlockMask)
103{
104 std::stack<Addr>& locked_addr_stack = locked_addrs[xc->contextId()];
105
99 // Normally RISC-V uses zero to indicate success and nonzero to indicate
100 // failure (right now only 1 is reserved), but in gem5 zero indicates
101 // failure and one indicates success, so here we conform to that (it should
102 // be switched in the instruction's implementation)
103
104 DPRINTF(LLSC, "[cid:%d]: locked_addrs empty? %s.\n", req->contextId(),
106 // Normally RISC-V uses zero to indicate success and nonzero to indicate
107 // failure (right now only 1 is reserved), but in gem5 zero indicates
108 // failure and one indicates success, so here we conform to that (it should
109 // be switched in the instruction's implementation)
110
111 DPRINTF(LLSC, "[cid:%d]: locked_addrs empty? %s.\n", req->contextId(),
105 locked_addrs.empty() ? "yes" : "no");
106 if (!locked_addrs.empty()) {
112 locked_addr_stack.empty() ? "yes" : "no");
113 if (!locked_addr_stack.empty()) {
107 DPRINTF(LLSC, "[cid:%d]: addr = %x.\n", req->contextId(),
108 req->getPaddr() & ~0xF);
109 DPRINTF(LLSC, "[cid:%d]: last locked addr = %x.\n", req->contextId(),
114 DPRINTF(LLSC, "[cid:%d]: addr = %x.\n", req->contextId(),
115 req->getPaddr() & ~0xF);
116 DPRINTF(LLSC, "[cid:%d]: last locked addr = %x.\n", req->contextId(),
110 locked_addrs.top());
117 locked_addr_stack.top());
111 }
118 }
112 if (locked_addrs.empty()
113 || locked_addrs.top() != ((req->getPaddr() & ~0xF))) {
119 if (locked_addr_stack.empty()
120 || locked_addr_stack.top() != ((req->getPaddr() & ~0xF))) {
114 req->setExtraData(0);
115 int stCondFailures = xc->readStCondFailures();
116 xc->setStCondFailures(++stCondFailures);
117 if (stCondFailures % WARN_FAILURE == 0) {
118 warn("%i: context %d: %d consecutive SC failures.\n",
119 curTick(), xc->contextId(), stCondFailures);
120 }
121 return false;

--- 17 unchanged lines hidden --- 		121 req->setExtraData(0);
122 int stCondFailures = xc->readStCondFailures();
123 xc->setStCondFailures(++stCondFailures);
124 if (stCondFailures % WARN_FAILURE == 0) {
125 warn("%i: context %d: %d consecutive SC failures.\n",
126 curTick(), xc->contextId(), stCondFailures);
127 }
128 return false;

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