locked_mem.hh (12748:ae5ce8e42de7) locked_mem.hh (12749:223c83ed9979)
1/*
2 * Copyright (c) 2006 The Regents of The University of Michigan
3 * Copyright (c) 2007-2008 The Florida State University
4 * Copyright (c) 2009 The University of Edinburgh
5 * Copyright (c) 2012 ARM Limited
6 * Copyright (c) 2014-2015 Sven Karlsson
7 * All rights reserved.
8 *

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77 Addr snoop_addr = pkt->getAddr() & cacheBlockMask;
78 DPRINTF(LLSC, "Locked snoop on address %x.\n", snoop_addr);
79 if ((locked_addrs.top() & cacheBlockMask) == snoop_addr)
80 locked_addrs.pop();
81}
82
83
84template <class XC> inline void
1/*
2 * Copyright (c) 2006 The Regents of The University of Michigan
3 * Copyright (c) 2007-2008 The Florida State University
4 * Copyright (c) 2009 The University of Edinburgh
5 * Copyright (c) 2012 ARM Limited
6 * Copyright (c) 2014-2015 Sven Karlsson
7 * All rights reserved.
8 *

--- 68 unchanged lines hidden (view full) ---

77 Addr snoop_addr = pkt->getAddr() & cacheBlockMask;
78 DPRINTF(LLSC, "Locked snoop on address %x.\n", snoop_addr);
79 if ((locked_addrs.top() & cacheBlockMask) == snoop_addr)
80 locked_addrs.pop();
81}
82
83
84template <class XC> inline void
85handleLockedRead(XC *xc, RequestPtr req)
85handleLockedRead(XC *xc, const RequestPtr &req)
86{
87 locked_addrs.push(req->getPaddr() & ~0xF);
88 DPRINTF(LLSC, "[cid:%d]: Reserved address %x.\n",
89 req->contextId(), req->getPaddr() & ~0xF);
90}
91
92template <class XC> inline void
93handleLockedSnoopHit(XC *xc)
94{}
95
96template <class XC> inline bool
86{
87 locked_addrs.push(req->getPaddr() & ~0xF);
88 DPRINTF(LLSC, "[cid:%d]: Reserved address %x.\n",
89 req->contextId(), req->getPaddr() & ~0xF);
90}
91
92template <class XC> inline void
93handleLockedSnoopHit(XC *xc)
94{}
95
96template <class XC> inline bool
97handleLockedWrite(XC *xc, RequestPtr req, Addr cacheBlockMask)
97handleLockedWrite(XC *xc, const RequestPtr &req, Addr cacheBlockMask)
98{
99 // Normally RISC-V uses zero to indicate success and nonzero to indicate
100 // failure (right now only 1 is reserved), but in gem5 zero indicates
101 // failure and one indicates success, so here we conform to that (it should
102 // be switched in the instruction's implementation)
103
104 DPRINTF(LLSC, "[cid:%d]: locked_addrs empty? %s.\n", req->contextId(),
105 locked_addrs.empty() ? "yes" : "no");

--- 33 unchanged lines hidden --- 		98{
99 // Normally RISC-V uses zero to indicate success and nonzero to indicate
100 // failure (right now only 1 is reserved), but in gem5 zero indicates
101 // failure and one indicates success, so here we conform to that (it should
102 // be switched in the instruction's implementation)
103
104 DPRINTF(LLSC, "[cid:%d]: locked_addrs empty? %s.\n", req->contextId(),
105 locked_addrs.empty() ? "yes" : "no");

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