locked_mem.hh (11723:0596db108c53) locked_mem.hh (11727:055ae402fbd0)
1/*
1/*
2 * Copyright (c) 2006 The Regents of The University of Michigan
3 * Copyright (c) 2007-2008 The Florida State University
4 * Copyright (c) 2009 The University of Edinburgh
2 * Copyright (c) 2006 The Regents of The University of Michigan
3 * Copyright (c) 2007-2008 The Florida State University
4 * Copyright (c) 2009 The University of Edinburgh
5 * Copyright (c) 2012 ARM Limited
6 * Copyright (c) 2014-2015 Sven Karlsson
5 * All rights reserved.
6 *
7 * All rights reserved.
8 *
9 * The license below extends only to copyright in the software and shall
10 * not be construed as granting a license to any other intellectual
11 * property including but not limited to intellectual property relating
12 * to a hardware implementation of the functionality of the software
13 * licensed hereunder. You may use the software subject to the license
14 * terms below provided that you ensure that this notice is replicated
15 * unmodified and in its entirety in all distributions of the software,
16 * modified or unmodified, in source code or in binary form.
17 *
18 * Copyright (c) 2006-2007 The Regents of The University of Michigan
19 * Copyright (c) 2016 The University of Virginia
20 * All rights reserved.
21 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions are
9 * met: redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer;
11 * redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution;
14 * neither the name of the copyright holders nor the names of its

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23 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
24 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
25 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
26 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
27 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
28 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
29 *
30 * Authors: Steve Reinhardt
22 * Redistribution and use in source and binary forms, with or without
23 * modification, are permitted provided that the following conditions are
24 * met: redistributions of source code must retain the above copyright
25 * notice, this list of conditions and the following disclaimer;
26 * redistributions in binary form must reproduce the above copyright
27 * notice, this list of conditions and the following disclaimer in the
28 * documentation and/or other materials provided with the distribution;
29 * neither the name of the copyright holders nor the names of its

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38 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
39 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
40 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
41 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
42 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
43 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
44 *
45 * Authors: Steve Reinhardt
31 * Stephen Hines
32 * Timothy M. Jones
46 * Alec Roelke
33 */
47 */
34
35#ifndef __ARCH_RISCV_LOCKED_MEM_HH__
36#define __ARCH_RISCV_LOCKED_MEM_HH__
37
48#ifndef __ARCH_RISCV_LOCKED_MEM_HH__
49#define __ARCH_RISCV_LOCKED_MEM_HH__
50
38/**
39 * @file
40 *
41 * ISA-specific helper functions for locked memory accesses.
42 */
43
51#include "arch/registers.hh"
52#include "base/misc.hh"
53#include "base/trace.hh"
54#include "debug/LLSC.hh"
44#include "mem/packet.hh"
45#include "mem/request.hh"
46
55#include "mem/packet.hh"
56#include "mem/request.hh"
57
58/*
59 * ISA-specific helper functions for locked memory accesses.
60 */
47namespace RiscvISA
48{
61namespace RiscvISA
62{
63static bool lock_flag = false;
64static Addr lock_addr = 0;
49
50template <class XC>
65
66template <class XC>
51inline void
52handleLockedSnoop(XC *xc, PacketPtr pkt, Addr cacheBlockMask)
67inline void handleLockedSnoop(XC *xc, PacketPtr pkt, Addr cacheBlockMask)
53{
68{
69 if (!lock_flag)
70 return;
71
72 DPRINTF(LLSC, "Locked snoop on address %x.\n",
73 pkt->getAddr()&cacheBlockMask);
74
75 Addr snoop_addr = pkt->getAddr()&cacheBlockMask;
76
77 if ((lock_addr&cacheBlockMask) == snoop_addr)
78 lock_flag = false;
54}
55
79}
80
81
56template <class XC>
82template <class XC>
57inline void
58handleLockedRead(XC *xc, Request *req)
83inline void handleLockedRead(XC *xc, Request *req)
59{
84{
85 lock_addr = req->getPaddr()&~0xF;
86 lock_flag = true;
87 DPRINTF(LLSC, "[cid:%i]: "
88 "Load-Link Flag Set & Load-Link Address set to %x.\n",
89 req->contextId(), req->getPaddr()&~0xF);
60}
61
62template <class XC>
90}
91
92template <class XC>
63inline void
64handleLockedSnoopHit(XC *xc)
65{
66}
93inline void handleLockedSnoopHit(XC *xc)
94{}
67
68template <class XC>
95
96template <class XC>
69inline bool
70handleLockedWrite(XC *xc, Request *req, Addr cacheBlockMask)
97inline bool handleLockedWrite(XC *xc, Request *req, Addr cacheBlockMask)
71{
98{
99 if (req->isUncacheable()) {
100 // Funky Turbolaser mailbox access...don't update
101 // result register (see stq_c in decoder.isa)
102 req->setExtraData(2);
103 } else {
104 // standard store conditional
105 if (!lock_flag || (req->getPaddr()&~0xF) != lock_addr) {
106 // Lock flag not set or addr mismatch in CPU;
107 // don't even bother sending to memory system
108 req->setExtraData(0);
109 lock_flag = false;
110
111 // the rest of this code is not architectural;
112 // it's just a debugging aid to help detect
113 // livelock by warning on long sequences of failed
114 // store conditionals
115 int stCondFailures = xc->readStCondFailures();
116 stCondFailures++;
117 xc->setStCondFailures(stCondFailures);
118 if (stCondFailures % 100000 == 0) {
119 warn("%i:"" context %d:"
120 " %d consecutive store conditional failures\n",
121 curTick(), xc->contextId(), stCondFailures);
122 }
123
124 if (!lock_flag){
125 DPRINTF(LLSC, "[cid:%i]:"
126 " Lock Flag Set, Store Conditional Failed.\n",
127 req->contextId());
128 } else if ((req->getPaddr() & ~0xf) != lock_addr) {
129 DPRINTF(LLSC, "[cid:%i]: Load-Link Address Mismatch, "
130 "Store Conditional Failed.\n", req->contextId());
131 }
132 // store conditional failed already, so don't issue it to mem
133 return false;
134 }
135 }
136
72 return true;
73}
74
75} // namespace RiscvISA
76
77#endif // __ARCH_RISCV_LOCKED_MEM_HH__
137 return true;
138}
139
140} // namespace RiscvISA
141
142#endif // __ARCH_RISCV_LOCKED_MEM_HH__