isa_traits.hh (12408:51e487705276) isa_traits.hh (12427:b0611f1ad833)
1/*
2 * Copyright (c) 2013 ARM Limited
3 * Copyright (c) 2014-2015 Sven Karlsson
4 * All rights reserved
5 *
6 * The license below extends only to copyright in the software and shall
7 * not be construed as granting a license to any other intellectual
8 * property including but not limited to intellectual property relating

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52
53namespace LittleEndianGuest {}
54
55namespace RiscvISA
56{
57
58using namespace LittleEndianGuest;
59
1/*
2 * Copyright (c) 2013 ARM Limited
3 * Copyright (c) 2014-2015 Sven Karlsson
4 * All rights reserved
5 *
6 * The license below extends only to copyright in the software and shall
7 * not be construed as granting a license to any other intellectual
8 * property including but not limited to intellectual property relating

--- 43 unchanged lines hidden (view full) ---

52
53namespace LittleEndianGuest {}
54
55namespace RiscvISA
56{
57
58using namespace LittleEndianGuest;
59
60// Riscv does NOT have a delay slot
61#define ISA_HAS_DELAY_SLOT 0
62
63const Addr PageShift = 12;
64const Addr PageBytes = ULL(1) << PageShift;
65
66// Memory accesses can be unaligned (at least for double-word memory accesses)
67const bool HasUnalignedMemAcc = true;
68
69const bool CurThreadInfoImplemented = false;
70const int CurThreadInfoReg = -1;
71
72}
73
74#endif //__ARCH_RISCV_ISA_TRAITS_HH__
60const Addr PageShift = 12;
61const Addr PageBytes = ULL(1) << PageShift;
62
63// Memory accesses can be unaligned (at least for double-word memory accesses)
64const bool HasUnalignedMemAcc = true;
65
66const bool CurThreadInfoImplemented = false;
67const int CurThreadInfoReg = -1;
68
69}
70
71#endif //__ARCH_RISCV_ISA_TRAITS_HH__