1/*
2 * Copyright (c) 2013 ARM Limited
3 * Copyright (c) 2014-2015 Sven Karlsson
4 * All rights reserved
5 *
6 * The license below extends only to copyright in the software and shall
7 * not be construed as granting a license to any other intellectual
8 * property including but not limited to intellectual property relating

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60// Riscv does NOT have a delay slot
61#define ISA_HAS_DELAY_SLOT 0
62
63const Addr PageShift = 12;
64const Addr PageBytes = ULL(1) << PageShift;
65
66const ExtMachInst NoopMachInst = 0x00000013;
67
68// Memory accesses can be unaligned (at least for double-word memory accesses)
69const bool HasUnalignedMemAcc = true;
70
71const bool CurThreadInfoImplemented = false;
72const int CurThreadInfoReg = -1;
73
74}
75
76#endif //__ARCH_RISCV_ISA_TRAITS_HH__