operands.isa (11726:11950d45640b) operands.isa (12120:133620bfc43b)
1// -*- mode:c++ -*-
2
3// Copyright (c) 2015 RISC-V Foundation
4// Copyright (c) 2016 The University of Virginia
5// All rights reserved.
6//
7// Redistribution and use in source and binary forms, with or without
8// modification, are permitted provided that the following conditions are

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44}};
45
46def operands {{
47#General Purpose Integer Reg Operands
48 'Rd': ('IntReg', 'ud', 'RD', 'IsInteger', 1),
49 'Rs1': ('IntReg', 'ud', 'RS1', 'IsInteger', 2),
50 'Rs2': ('IntReg', 'ud', 'RS2', 'IsInteger', 3),
51 'Rt': ('IntReg', 'ud', 'AMOTempReg', 'IsInteger', 4),
1// -*- mode:c++ -*-
2
3// Copyright (c) 2015 RISC-V Foundation
4// Copyright (c) 2016 The University of Virginia
5// All rights reserved.
6//
7// Redistribution and use in source and binary forms, with or without
8// modification, are permitted provided that the following conditions are

--- 35 unchanged lines hidden (view full) ---

44}};
45
46def operands {{
47#General Purpose Integer Reg Operands
48 'Rd': ('IntReg', 'ud', 'RD', 'IsInteger', 1),
49 'Rs1': ('IntReg', 'ud', 'RS1', 'IsInteger', 2),
50 'Rs2': ('IntReg', 'ud', 'RS2', 'IsInteger', 3),
51 'Rt': ('IntReg', 'ud', 'AMOTempReg', 'IsInteger', 4),
52 'Rc1': ('IntReg', 'ud', 'RC1', 'IsInteger', 2),
53 'Rc2': ('IntReg', 'ud', 'RC2', 'IsInteger', 3),
54 'Rp1': ('IntReg', 'ud', 'RP1 + 8', 'IsInteger', 2),
55 'Rp2': ('IntReg', 'ud', 'RP2 + 8', 'IsInteger', 3),
56 'ra': ('IntReg', 'ud', 'ReturnAddrReg', 'IsInteger', 1),
57 'sp': ('IntReg', 'ud', 'StackPointerReg', 'IsInteger', 2),
52
53 'Fd': ('FloatReg', 'df', 'FD', 'IsFloating', 1),
54 'Fd_bits': ('FloatReg', 'ud', 'FD', 'IsFloating', 1),
55 'Fs1': ('FloatReg', 'df', 'FS1', 'IsFloating', 2),
56 'Fs1_bits': ('FloatReg', 'ud', 'FS1', 'IsFloating', 2),
57 'Fs2': ('FloatReg', 'df', 'FS2', 'IsFloating', 3),
58 'Fs2_bits': ('FloatReg', 'ud', 'FS2', 'IsFloating', 3),
59 'Fs3': ('FloatReg', 'df', 'FS3', 'IsFloating', 4),
60 'Fs3_bits': ('FloatReg', 'ud', 'FS3', 'IsFloating', 4),
58
59 'Fd': ('FloatReg', 'df', 'FD', 'IsFloating', 1),
60 'Fd_bits': ('FloatReg', 'ud', 'FD', 'IsFloating', 1),
61 'Fs1': ('FloatReg', 'df', 'FS1', 'IsFloating', 2),
62 'Fs1_bits': ('FloatReg', 'ud', 'FS1', 'IsFloating', 2),
63 'Fs2': ('FloatReg', 'df', 'FS2', 'IsFloating', 3),
64 'Fs2_bits': ('FloatReg', 'ud', 'FS2', 'IsFloating', 3),
65 'Fs3': ('FloatReg', 'df', 'FS3', 'IsFloating', 4),
66 'Fs3_bits': ('FloatReg', 'ud', 'FS3', 'IsFloating', 4),
67 'Fc1': ('FloatReg', 'df', 'FC1', 'IsFloating', 1),
68 'Fc1_bits': ('FloatReg', 'ud', 'FC1', 'IsFloating', 1),
69 'Fc2': ('FloatReg', 'df', 'FC2', 'IsFloatReg', 2),
70 'Fc2_bits': ('FloatReg', 'ud', 'FC2', 'IsFloating', 2),
71 'Fp2': ('FloatReg', 'df', 'FP2 + 8', 'IsFloating', 2),
72 'Fp2_bits': ('FloatReg', 'ud', 'FP2 + 8', 'IsFloating', 2),
61
62#Memory Operand
63 'Mem': ('Mem', 'ud', None, ('IsMemRef', 'IsLoad', 'IsStore'), 5),
64
65#Program Counter Operands
66 'PC': ('PCState', 'ud', 'pc', (None, None, 'IsControl'), 7),
67 'NPC': ('PCState', 'ud', 'npc', (None, None, 'IsControl'), 8),
68}};
73
74#Memory Operand
75 'Mem': ('Mem', 'ud', None, ('IsMemRef', 'IsLoad', 'IsStore'), 5),
76
77#Program Counter Operands
78 'PC': ('PCState', 'ud', 'pc', (None, None, 'IsControl'), 7),
79 'NPC': ('PCState', 'ud', 'npc', (None, None, 'IsControl'), 8),
80}};