operands.isa (11723:0596db108c53) operands.isa (11725:eb58f1bbeac8)
1// -*- mode:c++ -*-
2
3// Copyright (c) 2015 RISC-V Foundation
4// Copyright (c) 2016 The University of Virginia
5// All rights reserved.
6//
7// Redistribution and use in source and binary forms, with or without
8// modification, are permitted provided that the following conditions are

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34 'sb' : 'int8_t',
35 'ub' : 'uint8_t',
36 'sh' : 'int16_t',
37 'uh' : 'uint16_t',
38 'sw' : 'int32_t',
39 'uw' : 'uint32_t',
40 'sd' : 'int64_t',
41 'ud' : 'uint64_t',
1// -*- mode:c++ -*-
2
3// Copyright (c) 2015 RISC-V Foundation
4// Copyright (c) 2016 The University of Virginia
5// All rights reserved.
6//
7// Redistribution and use in source and binary forms, with or without
8// modification, are permitted provided that the following conditions are

--- 25 unchanged lines hidden (view full) ---

34 'sb' : 'int8_t',
35 'ub' : 'uint8_t',
36 'sh' : 'int16_t',
37 'uh' : 'uint16_t',
38 'sw' : 'int32_t',
39 'uw' : 'uint32_t',
40 'sd' : 'int64_t',
41 'ud' : 'uint64_t',
42 'sf' : 'float',
43 'df' : 'double'
42}};
43
44def operands {{
45#General Purpose Integer Reg Operands
46 'Rd': ('IntReg', 'ud', 'RD', 'IsInteger', 1),
47 'Rs1': ('IntReg', 'ud', 'RS1', 'IsInteger', 2),
48 'Rs2': ('IntReg', 'ud', 'RS2', 'IsInteger', 3),
49
44}};
45
46def operands {{
47#General Purpose Integer Reg Operands
48 'Rd': ('IntReg', 'ud', 'RD', 'IsInteger', 1),
49 'Rs1': ('IntReg', 'ud', 'RS1', 'IsInteger', 2),
50 'Rs2': ('IntReg', 'ud', 'RS2', 'IsInteger', 3),
51
52 'Fd': ('FloatReg', 'df', 'FD', 'IsFloating', 1),
53 'Fd_bits': ('FloatReg', 'ud', 'FD', 'IsFloating', 1),
54 'Fs1': ('FloatReg', 'df', 'FS1', 'IsFloating', 2),
55 'Fs1_bits': ('FloatReg', 'ud', 'FS1', 'IsFloating', 2),
56 'Fs2': ('FloatReg', 'df', 'FS2', 'IsFloating', 3),
57 'Fs2_bits': ('FloatReg', 'ud', 'FS2', 'IsFloating', 3),
58 'Fs3': ('FloatReg', 'df', 'FS3', 'IsFloating', 4),
59 'Fs3_bits': ('FloatReg', 'ud', 'FS3', 'IsFloating', 4),
60
50#Memory Operand
51 'Mem': ('Mem', 'ud', None, ('IsMemRef', 'IsLoad', 'IsStore'), 5),
52
53#Program Counter Operands
54 'PC': ('PCState', 'ud', 'pc', (None, None, 'IsControl'), 7),
55 'NPC': ('PCState', 'ud', 'npc', (None, None, 'IsControl'), 8),
56}};
61#Memory Operand
62 'Mem': ('Mem', 'ud', None, ('IsMemRef', 'IsLoad', 'IsStore'), 5),
63
64#Program Counter Operands
65 'PC': ('PCState', 'ud', 'pc', (None, None, 'IsControl'), 7),
66 'NPC': ('PCState', 'ud', 'npc', (None, None, 'IsControl'), 8),
67}};