1// -*- mode:c++ -*- 2 3// Copyright (c) 2015 RISC-V Foundation 4// Copyright (c) 2016 The University of Virginia 5// All rights reserved. 6// 7// Redistribution and use in source and binary forms, with or without 8// modification, are permitted provided that the following conditions are --- 34 unchanged lines hidden (view full) --- 43 'df' : 'double' 44}}; 45 46def operands {{ 47#General Purpose Integer Reg Operands 48 'Rd': ('IntReg', 'ud', 'RD', 'IsInteger', 1), 49 'Rs1': ('IntReg', 'ud', 'RS1', 'IsInteger', 2), 50 'Rs2': ('IntReg', 'ud', 'RS2', 'IsInteger', 3), |
51 'Rt': ('IntReg', 'ud', 'AMOTempReg', 'IsInteger', 4), |
52 53 'Fd': ('FloatReg', 'df', 'FD', 'IsFloating', 1), 54 'Fd_bits': ('FloatReg', 'ud', 'FD', 'IsFloating', 1), 55 'Fs1': ('FloatReg', 'df', 'FS1', 'IsFloating', 2), 56 'Fs1_bits': ('FloatReg', 'ud', 'FS1', 'IsFloating', 2), 57 'Fs2': ('FloatReg', 'df', 'FS2', 'IsFloating', 3), 58 'Fs2_bits': ('FloatReg', 'ud', 'FS2', 'IsFloating', 3), 59 'Fs3': ('FloatReg', 'df', 'FS3', 'IsFloating', 4), 60 'Fs3_bits': ('FloatReg', 'ud', 'FS3', 'IsFloating', 4), 61 62#Memory Operand 63 'Mem': ('Mem', 'ud', None, ('IsMemRef', 'IsLoad', 'IsStore'), 5), 64 65#Program Counter Operands 66 'PC': ('PCState', 'ud', 'pc', (None, None, 'IsControl'), 7), 67 'NPC': ('PCState', 'ud', 'npc', (None, None, 'IsControl'), 8), 68}}; |