1// -*- mode:c++ -*-
2
3// Copyright (c) 2015 RISC-V Foundation
4// Copyright (c) 2016 The University of Virginia
5// All rights reserved.
6//
7// Redistribution and use in source and binary forms, with or without
8// modification, are permitted provided that the following conditions are

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34 'sb' : 'int8_t',
35 'ub' : 'uint8_t',
36 'sh' : 'int16_t',
37 'uh' : 'uint16_t',
38 'sw' : 'int32_t',
39 'uw' : 'uint32_t',
40 'sd' : 'int64_t',
41 'ud' : 'uint64_t',
42}};
43
44def operands {{
45#General Purpose Integer Reg Operands
46 'Rd': ('IntReg', 'ud', 'RD', 'IsInteger', 1),
47 'Rs1': ('IntReg', 'ud', 'RS1', 'IsInteger', 2),
48 'Rs2': ('IntReg', 'ud', 'RS2', 'IsInteger', 3),
49
50#Memory Operand
51 'Mem': ('Mem', 'ud', None, ('IsMemRef', 'IsLoad', 'IsStore'), 5),
52
53#Program Counter Operands
54 'PC': ('PCState', 'ud', 'pc', (None, None, 'IsControl'), 7),
55 'NPC': ('PCState', 'ud', 'npc', (None, None, 'IsControl'), 8),
56}};