Cross Reference: /gem5/src/arch/riscv/isa/main.isa

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main.isa (11723:0596db108c53)	main.isa (11726:11950d45640b)
1// -- mode:c++ -- 2 3// Copyright (c) 2015 RISC-V Foundation 4// Copyright (c) 2016 The University of Virginia 5// All rights reserved. 6// 7// Redistribution and use in source and binary forms, with or without 8// modification, are permitted provided that the following conditions are --- 42 unchanged lines hidden (view full) --- 51##include "bitfields.isa" 52 53//Include the operand_types and operand definitions 54##include "operands.isa" 55 56//Include the base class for riscv instructions, and some support code 57##include "base.isa" 58	1// -- mode:c++ -- 2 3// Copyright (c) 2015 RISC-V Foundation 4// Copyright (c) 2016 The University of Virginia 5// All rights reserved. 6// 7// Redistribution and use in source and binary forms, with or without 8// modification, are permitted provided that the following conditions are --- 42 unchanged lines hidden (view full) --- 51##include "bitfields.isa" 52 53//Include the operand_types and operand definitions 54##include "operands.isa" 55 56//Include the base class for riscv instructions, and some support code 57##include "base.isa" 58
	59// Include the base class for instructions with micro code 60##include "micro.isa" 61
59//Include the definitions for the instruction formats 60##include "formats/formats.isa" 61 62//Include the decoder definition 63##include "decoder.isa"	62//Include the definitions for the instruction formats 63##include "formats/formats.isa" 64 65//Include the decoder definition 66##include "decoder.isa"