includes.isa (11723:0596db108c53) includes.isa (11725:eb58f1bbeac8)
1// -*- mode:c++ -*-
2
3// Copyright (c) 2015 RISC-V Foundation
4// Copyright (c) 2016 The University of Virginia
5// All rights reserved.
6//
7// Redistribution and use in source and binary forms, with or without
8// modification, are permitted provided that the following conditions are

--- 54 unchanged lines hidden (view full) ---

63#include "mem/packet.hh"
64#include "mem/request.hh"
65#include "sim/full_system.hh"
66
67using namespace RiscvISA;
68}};
69
70output exec {{
1// -*- mode:c++ -*-
2
3// Copyright (c) 2015 RISC-V Foundation
4// Copyright (c) 2016 The University of Virginia
5// All rights reserved.
6//
7// Redistribution and use in source and binary forms, with or without
8// modification, are permitted provided that the following conditions are

--- 54 unchanged lines hidden (view full) ---

63#include "mem/packet.hh"
64#include "mem/request.hh"
65#include "sim/full_system.hh"
66
67using namespace RiscvISA;
68}};
69
70output exec {{
71#include <cfenv>
71#include <cmath>
72#include <string>
73
74#include "arch/generic/memhelpers.hh"
75#include "arch/riscv/faults.hh"
76#include "arch/riscv/registers.hh"
72#include <cmath>
73#include <string>
74
75#include "arch/generic/memhelpers.hh"
76#include "arch/riscv/faults.hh"
77#include "arch/riscv/registers.hh"
78#include "arch/riscv/utility.hh"
77#include "base/condcodes.hh"
78#include "cpu/base.hh"
79#include "cpu/exetrace.hh"
80#include "mem/packet.hh"
81#include "mem/packet_access.hh"
82#include "mem/request.hh"
83#include "sim/eventq.hh"
84#include "sim/full_system.hh"
85#include "sim/sim_events.hh"
86#include "sim/sim_exit.hh"
87#include "sim/system.hh"
88
89using namespace RiscvISA;
90}};
79#include "base/condcodes.hh"
80#include "cpu/base.hh"
81#include "cpu/exetrace.hh"
82#include "mem/packet.hh"
83#include "mem/packet_access.hh"
84#include "mem/request.hh"
85#include "sim/eventq.hh"
86#include "sim/full_system.hh"
87#include "sim/sim_events.hh"
88#include "sim/sim_exit.hh"
89#include "sim/system.hh"
90
91using namespace RiscvISA;
92}};