1// -*- mode:c++ -*- 2 3// Copyright (c) 2015 RISC-V Foundation 4// Copyright (c) 2016 The University of Virginia 5// All rights reserved. 6// 7// Redistribution and use in source and binary forms, with or without 8// modification, are permitted provided that the following conditions are --- 51 unchanged lines hidden (view full) --- 60#include "base/cprintf.hh" 61#include "base/loader/symtab.hh" 62#include "cpu/thread_context.hh" 63#include "mem/packet.hh" 64#include "mem/request.hh" 65#include "sim/full_system.hh" 66 67using namespace RiscvISA; |
68using namespace std; |
69}}; 70 71output exec {{ 72#include <cfenv> 73#include <cmath> 74#include <string> 75#include <vector> 76 --- 9 unchanged lines hidden (view full) --- 86#include "mem/request.hh" 87#include "sim/eventq.hh" 88#include "sim/full_system.hh" 89#include "sim/sim_events.hh" 90#include "sim/sim_exit.hh" 91#include "sim/system.hh" 92 93using namespace RiscvISA; |
94using namespace std; |
95}}; |