1// -*- mode:c++ -*-
2
3// Copyright (c) 2015 RISC-V Foundation
4// Copyright (c) 2016 The University of Virginia
5// All rights reserved.
6//
7// Redistribution and use in source and binary forms, with or without
8// modification, are permitted provided that the following conditions are

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60#include "base/cprintf.hh"
61#include "base/loader/symtab.hh"
62#include "cpu/thread_context.hh"
63#include "mem/packet.hh"
64#include "mem/request.hh"
65#include "sim/full_system.hh"
66
67using namespace RiscvISA;
68}};
69
70output exec {{
71#include <cfenv>
72#include <cmath>
73#include <string>
74#include <vector>
75

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85#include "mem/request.hh"
86#include "sim/eventq.hh"
87#include "sim/full_system.hh"
88#include "sim/sim_events.hh"
89#include "sim/sim_exit.hh"
90#include "sim/system.hh"
91
92using namespace RiscvISA;
93}};