standard.isa (12849:7f43ad13ebf0) standard.isa (13548:b76f99d052bb)
1// -*- mode:c++ -*-
2
3// Copyright (c) 2015 RISC-V Foundation
4// Copyright (c) 2016-2017 The University of Virginia
5// All rights reserved.
6//
7// Redistribution and use in source and binary forms, with or without
8// modification, are permitted provided that the following conditions are

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251 if (data != olddata) {
252 if (bits(csr, 11, 10) == 0x3) {
253 std::string error = csprintf("CSR %s is read-only\n",
254 CSRData.at(csr).name);
255 fault = make_shared<IllegalInstFault>(error, machInst);
256 } else {
257 DPRINTF(RiscvMisc, "Writing %#x to CSR %s.\n", data,
258 CSRData.at(csr).name);
1// -*- mode:c++ -*-
2
3// Copyright (c) 2015 RISC-V Foundation
4// Copyright (c) 2016-2017 The University of Virginia
5// All rights reserved.
6//
7// Redistribution and use in source and binary forms, with or without
8// modification, are permitted provided that the following conditions are

--- 242 unchanged lines hidden (view full) ---

251 if (data != olddata) {
252 if (bits(csr, 11, 10) == 0x3) {
253 std::string error = csprintf("CSR %s is read-only\n",
254 CSRData.at(csr).name);
255 fault = make_shared<IllegalInstFault>(error, machInst);
256 } else {
257 DPRINTF(RiscvMisc, "Writing %#x to CSR %s.\n", data,
258 CSRData.at(csr).name);
259 INTERRUPT oldinterrupt = olddata;
260 INTERRUPT newinterrupt = data;
259 switch (csr) {
260 case CSR_FCSR:
261 xc->setMiscReg(MISCREG_FFLAGS, bits(data, 4, 0));
262 xc->setMiscReg(MISCREG_FRM, bits(data, 7, 5));
263 break;
261 switch (csr) {
262 case CSR_FCSR:
263 xc->setMiscReg(MISCREG_FFLAGS, bits(data, 4, 0));
264 xc->setMiscReg(MISCREG_FRM, bits(data, 7, 5));
265 break;
266 case CSR_MIP: case CSR_MIE:
267 if (oldinterrupt.mei == newinterrupt.mei &&
268 oldinterrupt.mti == newinterrupt.mti &&
269 oldinterrupt.msi == newinterrupt.msi) {
270 xc->setMiscReg(CSRData.at(csr).physIndex,data);
271 } else {
272 std::string error = "Interrupt m bits are "
273 "read-only\n";
274 fault = make_shared<IllegalInstFault>(error,
275 machInst);
276 }
277 break;
264 default:
265 xc->setMiscReg(CSRData.at(csr).physIndex, data);
266 break;
267 }
268 }
269 }
270 }
271 if (fault == NoFault) {

--- 100 unchanged lines hidden --- 		278 default:
279 xc->setMiscReg(CSRData.at(csr).physIndex, data);
280 break;
281 }
282 }
283 }
284 }
285 if (fault == NoFault) {

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