standard.isa (12320:d846aaaa33b1) standard.isa (12328:95ba4611788a)
1// -*- mode:c++ -*-
2
3// Copyright (c) 2015 RISC-V Foundation
4// Copyright (c) 2016-2017 The University of Virginia
5// All rights reserved.
6//
7// Redistribution and use in source and binary forms, with or without
8// modification, are permitted provided that the following conditions are

--- 205 unchanged lines hidden (view full) ---

214 iop = InstObjParams(name, Name, 'RegOp', code, opt_flags)
215 header_output = BasicDeclare.subst(iop)
216 decoder_output = BasicConstructor.subst(iop)
217 decode_block = BasicDecode.subst(iop)
218 exec_output = BasicExecute.subst(iop)
219}};
220
221def format IOp(code, *opt_flags) {{
1// -*- mode:c++ -*-
2
3// Copyright (c) 2015 RISC-V Foundation
4// Copyright (c) 2016-2017 The University of Virginia
5// All rights reserved.
6//
7// Redistribution and use in source and binary forms, with or without
8// modification, are permitted provided that the following conditions are

--- 205 unchanged lines hidden (view full) ---

214 iop = InstObjParams(name, Name, 'RegOp', code, opt_flags)
215 header_output = BasicDeclare.subst(iop)
216 decoder_output = BasicConstructor.subst(iop)
217 decode_block = BasicDecode.subst(iop)
218 exec_output = BasicExecute.subst(iop)
219}};
220
221def format IOp(code, *opt_flags) {{
222 imm_code = 'imm = IMM12; if (IMMSIGN > 0) imm |= ~((uint64_t)0x7FF);'
223 regs = ['_destRegIdx[0]','_srcRegIdx[0]']
224 iop = InstObjParams(name, Name, 'ImmOp<int64_t>',
222 regs = ['_destRegIdx[0]','_srcRegIdx[0]']
223 iop = InstObjParams(name, Name, 'ImmOp<int64_t>',
225 {'code': code, 'imm_code': imm_code,
224 {'code': code, 'imm_code': 'imm = sext<12>(IMM12);',
226 'regs': ','.join(regs)}, opt_flags)
227 header_output = ImmDeclare.subst(iop)
228 decoder_output = ImmConstructor.subst(iop)
229 decode_block = BasicDecode.subst(iop)
230 exec_output = ImmExecute.subst(iop)
231}};
232
233def format BOp(code, *opt_flags) {{
234 imm_code = """
225 'regs': ','.join(regs)}, opt_flags)
226 header_output = ImmDeclare.subst(iop)
227 decoder_output = ImmConstructor.subst(iop)
228 decode_block = BasicDecode.subst(iop)
229 exec_output = ImmExecute.subst(iop)
230}};
231
232def format BOp(code, *opt_flags) {{
233 imm_code = """
235 imm |= BIMM12BIT11 << 11;
236 imm |= BIMM12BITS4TO1 << 1;
237 imm |= BIMM12BITS10TO5 << 5;
238 if (IMMSIGN > 0)
239 imm |= ~((uint64_t)0xFFF);
234 imm = BIMM12BITS4TO1 << 1 |
235 BIMM12BITS10TO5 << 5 |
236 BIMM12BIT11 << 11 |
237 IMMSIGN << 12;
238 imm = sext<13>(imm);
240 """
241 regs = ['_srcRegIdx[0]','_srcRegIdx[1]']
242 iop = InstObjParams(name, Name, 'ImmOp<int64_t>',
243 {'code': code, 'imm_code': imm_code,
244 'regs': ','.join(regs)}, opt_flags)
245 header_output = BranchDeclare.subst(iop)
246 decoder_output = ImmConstructor.subst(iop)
247 decode_block = BasicDecode.subst(iop)
248 exec_output = BranchExecute.subst(iop)
249}};
250
251def format Jump(code, *opt_flags) {{
239 """
240 regs = ['_srcRegIdx[0]','_srcRegIdx[1]']
241 iop = InstObjParams(name, Name, 'ImmOp<int64_t>',
242 {'code': code, 'imm_code': imm_code,
243 'regs': ','.join(regs)}, opt_flags)
244 header_output = BranchDeclare.subst(iop)
245 decoder_output = ImmConstructor.subst(iop)
246 decode_block = BasicDecode.subst(iop)
247 exec_output = BranchExecute.subst(iop)
248}};
249
250def format Jump(code, *opt_flags) {{
252 imm_code = 'imm = IMM12; if (IMMSIGN > 0) imm |= ~((uint64_t)0x7FF);'
253 regs = ['_destRegIdx[0]','_srcRegIdx[0]']
251 regs = ['_destRegIdx[0]', '_srcRegIdx[0]']
254 iop = InstObjParams(name, Name, 'ImmOp<int64_t>',
252 iop = InstObjParams(name, Name, 'ImmOp<int64_t>',
255 {'code': code, 'imm_code': imm_code,
253 {'code': code, 'imm_code': 'imm = sext<12>(IMM12);',
256 'regs': ','.join(regs)}, opt_flags)
257 header_output = JumpDeclare.subst(iop)
258 decoder_output = ImmConstructor.subst(iop)
259 decode_block = BasicDecode.subst(iop)
260 exec_output = JumpExecute.subst(iop)
261}};
262
263def format UOp(code, *opt_flags) {{
254 'regs': ','.join(regs)}, opt_flags)
255 header_output = JumpDeclare.subst(iop)
256 decoder_output = ImmConstructor.subst(iop)
257 decode_block = BasicDecode.subst(iop)
258 exec_output = JumpExecute.subst(iop)
259}};
260
261def format UOp(code, *opt_flags) {{
264 imm_code = 'imm = (int32_t)(IMM20 << 12);'
265 regs = ['_destRegIdx[0]']
266 iop = InstObjParams(name, Name, 'ImmOp<int64_t>',
262 regs = ['_destRegIdx[0]']
263 iop = InstObjParams(name, Name, 'ImmOp<int64_t>',
267 {'code': code, 'imm_code': imm_code,
264 {'code': code, 'imm_code': 'imm = sext<20>(IMM20) << 12;',
268 'regs': ','.join(regs)}, opt_flags)
269 header_output = ImmDeclare.subst(iop)
270 decoder_output = ImmConstructor.subst(iop)
271 decode_block = BasicDecode.subst(iop)
272 exec_output = ImmExecute.subst(iop)
273}};
274
275def format JOp(code, *opt_flags) {{
276 imm_code = """
265 'regs': ','.join(regs)}, opt_flags)
266 header_output = ImmDeclare.subst(iop)
267 decoder_output = ImmConstructor.subst(iop)
268 decode_block = BasicDecode.subst(iop)
269 exec_output = ImmExecute.subst(iop)
270}};
271
272def format JOp(code, *opt_flags) {{
273 imm_code = """
277 imm |= UJIMMBITS19TO12 << 12;
278 imm |= UJIMMBIT11 << 11;
279 imm |= UJIMMBITS10TO1 << 1;
280 if (IMMSIGN > 0)
281 imm |= ~((uint64_t)0xFFFFF);
274 imm = UJIMMBITS10TO1 << 1 |
275 UJIMMBIT11 << 11 |
276 UJIMMBITS19TO12 << 12 |
277 IMMSIGN << 20;
278 imm = sext<21>(imm);
282 """
283 pc = 'pc.set(pc.pc() + imm);'
284 regs = ['_destRegIdx[0]']
285 iop = InstObjParams(name, Name, 'ImmOp<int64_t>',
286 {'code': code, 'imm_code': imm_code,
287 'regs': ','.join(regs)}, opt_flags)
288 header_output = BranchDeclare.subst(iop)
289 decoder_output = ImmConstructor.subst(iop)

--- 19 unchanged lines hidden --- 		279 """
280 pc = 'pc.set(pc.pc() + imm);'
281 regs = ['_destRegIdx[0]']
282 iop = InstObjParams(name, Name, 'ImmOp<int64_t>',
283 {'code': code, 'imm_code': imm_code,
284 'regs': ','.join(regs)}, opt_flags)
285 header_output = BranchDeclare.subst(iop)
286 decoder_output = ImmConstructor.subst(iop)

--- 19 unchanged lines hidden ---