standard.isa (12236:126ac9da6050) standard.isa (12320:d846aaaa33b1)
1// -*- mode:c++ -*-
2
3// Copyright (c) 2015 RISC-V Foundation
4// Copyright (c) 2016-2017 The University of Virginia
5// All rights reserved.
6//
7// Redistribution and use in source and binary forms, with or without
8// modification, are permitted provided that the following conditions are

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28// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
29//
30// Authors: Alec Roelke
31
32////////////////////////////////////////////////////////////////////
33//
34// Integer instructions
35//
1// -*- mode:c++ -*-
2
3// Copyright (c) 2015 RISC-V Foundation
4// Copyright (c) 2016-2017 The University of Virginia
5// All rights reserved.
6//
7// Redistribution and use in source and binary forms, with or without
8// modification, are permitted provided that the following conditions are

--- 19 unchanged lines hidden (view full) ---

28// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
29//
30// Authors: Alec Roelke
31
32////////////////////////////////////////////////////////////////////
33//
34// Integer instructions
35//
36output header {{
37 /**
38 * Base class for operations that work only on registers
39 */
40 class RegOp : public RiscvStaticInst
41 {
42 protected:
43 /// Constructor
44 RegOp(const char *mnem, MachInst _machInst, OpClass __opClass)
45 : RiscvStaticInst(mnem, _machInst, __opClass)
46 {}
47
36
48 std::string
49 generateDisassembly(Addr pc, const SymbolTable *symtab) const;
50 };
51
52 /**
53 * Base class for operations with signed immediates
54 */
55 class ImmOp : public RiscvStaticInst
56 {
57 protected:
58 int64_t imm;
59
60 /// Constructor
61 ImmOp(const char *mnem, MachInst _machInst, OpClass __opClass)
62 : RiscvStaticInst(mnem, _machInst, __opClass), imm(0)
63 {}
64
65 virtual std::string
66 generateDisassembly(Addr pc, const SymbolTable *symtab) const = 0;
67 };
68
69 /**
70 * Base class for operations with unsigned immediates
71 */
72 class UImmOp : public RiscvStaticInst
73 {
74 protected:
75 uint64_t imm;
76
77 /// Constructor
78 UImmOp(const char *mnem, MachInst _machInst, OpClass __opClass)
79 : RiscvStaticInst(mnem, _machInst, __opClass), imm(0)
80 {}
81
82 virtual std::string
83 generateDisassembly(Addr pc, const SymbolTable *symtab) const = 0;
84 };
85
86 /**
87 * Base class for operations with branching
88 */
89 class BranchOp : public ImmOp
90 {
91 protected:
92 /// Constructor
93 BranchOp(const char *mnem, MachInst _machInst, OpClass __opClass)
94 : ImmOp(mnem, _machInst, __opClass)
95 {}
96
97 using StaticInst::branchTarget;
98
99 virtual RiscvISA::PCState
100 branchTarget(ThreadContext *tc) const
101 {
102 return StaticInst::branchTarget(tc);
103 }
104
105 virtual RiscvISA::PCState
106 branchTarget(const RiscvISA::PCState &branchPC) const
107 {
108 return StaticInst::branchTarget(branchPC);
109 }
110
111 virtual std::string
112 generateDisassembly(Addr pc, const SymbolTable *symtab) const = 0;
113 };
114
115 /**
116 * Base class for system operations
117 */
118 class SystemOp : public RiscvStaticInst
119 {
120 public:
121 /// Constructor
122 SystemOp(const char *mnem, MachInst _machInst, OpClass __opClass)
123 : RiscvStaticInst(mnem, _machInst, __opClass)
124 {}
125
126 std::string
127 generateDisassembly(Addr pc, const SymbolTable *symtab) const
128 {
129 return mnemonic;
130 }
131 };
132
133 /**
134 * Base class for CSR operations
135 */
136 class CSROp : public RiscvStaticInst
137 {
138 protected:
139 uint64_t csr;
140 uint64_t uimm;
141
142 public:
143 /// Constructor
144 CSROp(const char *mnem, MachInst _machInst, OpClass __opClass)
145 : RiscvStaticInst(mnem, _machInst, __opClass),
146 csr(FUNCT12), uimm(CSRIMM)
147 {}
148
149 std::string
150 generateDisassembly(Addr pc, const SymbolTable *symtab) const;
151 };
152}};
153
154//Outputs to decoder.cc
155output decoder {{
156 std::string
157 RegOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
158 {
159 std::stringstream ss;
160 ss << mnemonic << ' ' << registerName(_destRegIdx[0]) << ", " <<
161 registerName(_srcRegIdx[0]) << ", " <<
162 registerName(_srcRegIdx[1]);
163 return ss.str();
164 }
165
166 std::string
167 CSROp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
168 {
169 std::stringstream ss;
170 ss << mnemonic << ' ' << registerName(_destRegIdx[0]) << ", ";
171 if (_numSrcRegs > 0)
172 ss << registerName(_srcRegIdx[0]) << ", ";
173 ss << MiscRegNames.at(csr);
174 return ss.str();
175 }
176}};
177
178def template ImmDeclare {{
179 //
180 // Static instruction class for "%(mnemonic)s".
181 //
182 class %(class_name)s : public %(base_class)s
183 {
184 public:
185 /// Constructor.

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357 decoder_output = BasicConstructor.subst(iop)
358 decode_block = BasicDecode.subst(iop)
359 exec_output = BasicExecute.subst(iop)
360}};
361
362def format IOp(code, *opt_flags) {{
363 imm_code = 'imm = IMM12; if (IMMSIGN > 0) imm |= ~((uint64_t)0x7FF);'
364 regs = ['_destRegIdx[0]','_srcRegIdx[0]']
37def template ImmDeclare {{
38 //
39 // Static instruction class for "%(mnemonic)s".
40 //
41 class %(class_name)s : public %(base_class)s
42 {
43 public:
44 /// Constructor.

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216 decoder_output = BasicConstructor.subst(iop)
217 decode_block = BasicDecode.subst(iop)
218 exec_output = BasicExecute.subst(iop)
219}};
220
221def format IOp(code, *opt_flags) {{
222 imm_code = 'imm = IMM12; if (IMMSIGN > 0) imm |= ~((uint64_t)0x7FF);'
223 regs = ['_destRegIdx[0]','_srcRegIdx[0]']
365 iop = InstObjParams(name, Name, 'ImmOp',
224 iop = InstObjParams(name, Name, 'ImmOp<int64_t>',
366 {'code': code, 'imm_code': imm_code,
367 'regs': ','.join(regs)}, opt_flags)
368 header_output = ImmDeclare.subst(iop)
369 decoder_output = ImmConstructor.subst(iop)
370 decode_block = BasicDecode.subst(iop)
371 exec_output = ImmExecute.subst(iop)
372}};
373
374def format BOp(code, *opt_flags) {{
375 imm_code = """
376 imm |= BIMM12BIT11 << 11;
377 imm |= BIMM12BITS4TO1 << 1;
378 imm |= BIMM12BITS10TO5 << 5;
379 if (IMMSIGN > 0)
380 imm |= ~((uint64_t)0xFFF);
381 """
382 regs = ['_srcRegIdx[0]','_srcRegIdx[1]']
225 {'code': code, 'imm_code': imm_code,
226 'regs': ','.join(regs)}, opt_flags)
227 header_output = ImmDeclare.subst(iop)
228 decoder_output = ImmConstructor.subst(iop)
229 decode_block = BasicDecode.subst(iop)
230 exec_output = ImmExecute.subst(iop)
231}};
232
233def format BOp(code, *opt_flags) {{
234 imm_code = """
235 imm |= BIMM12BIT11 << 11;
236 imm |= BIMM12BITS4TO1 << 1;
237 imm |= BIMM12BITS10TO5 << 5;
238 if (IMMSIGN > 0)
239 imm |= ~((uint64_t)0xFFF);
240 """
241 regs = ['_srcRegIdx[0]','_srcRegIdx[1]']
383 iop = InstObjParams(name, Name, 'BranchOp',
242 iop = InstObjParams(name, Name, 'ImmOp<int64_t>',
384 {'code': code, 'imm_code': imm_code,
385 'regs': ','.join(regs)}, opt_flags)
386 header_output = BranchDeclare.subst(iop)
387 decoder_output = ImmConstructor.subst(iop)
388 decode_block = BasicDecode.subst(iop)
389 exec_output = BranchExecute.subst(iop)
390}};
391
392def format Jump(code, *opt_flags) {{
393 imm_code = 'imm = IMM12; if (IMMSIGN > 0) imm |= ~((uint64_t)0x7FF);'
394 regs = ['_destRegIdx[0]','_srcRegIdx[0]']
243 {'code': code, 'imm_code': imm_code,
244 'regs': ','.join(regs)}, opt_flags)
245 header_output = BranchDeclare.subst(iop)
246 decoder_output = ImmConstructor.subst(iop)
247 decode_block = BasicDecode.subst(iop)
248 exec_output = BranchExecute.subst(iop)
249}};
250
251def format Jump(code, *opt_flags) {{
252 imm_code = 'imm = IMM12; if (IMMSIGN > 0) imm |= ~((uint64_t)0x7FF);'
253 regs = ['_destRegIdx[0]','_srcRegIdx[0]']
395 iop = InstObjParams(name, Name, 'BranchOp',
254 iop = InstObjParams(name, Name, 'ImmOp<int64_t>',
396 {'code': code, 'imm_code': imm_code,
397 'regs': ','.join(regs)}, opt_flags)
398 header_output = JumpDeclare.subst(iop)
399 decoder_output = ImmConstructor.subst(iop)
400 decode_block = BasicDecode.subst(iop)
401 exec_output = JumpExecute.subst(iop)
402}};
403
404def format UOp(code, *opt_flags) {{
405 imm_code = 'imm = (int32_t)(IMM20 << 12);'
406 regs = ['_destRegIdx[0]']
255 {'code': code, 'imm_code': imm_code,
256 'regs': ','.join(regs)}, opt_flags)
257 header_output = JumpDeclare.subst(iop)
258 decoder_output = ImmConstructor.subst(iop)
259 decode_block = BasicDecode.subst(iop)
260 exec_output = JumpExecute.subst(iop)
261}};
262
263def format UOp(code, *opt_flags) {{
264 imm_code = 'imm = (int32_t)(IMM20 << 12);'
265 regs = ['_destRegIdx[0]']
407 iop = InstObjParams(name, Name, 'ImmOp',
266 iop = InstObjParams(name, Name, 'ImmOp<int64_t>',
408 {'code': code, 'imm_code': imm_code,
409 'regs': ','.join(regs)}, opt_flags)
410 header_output = ImmDeclare.subst(iop)
411 decoder_output = ImmConstructor.subst(iop)
412 decode_block = BasicDecode.subst(iop)
413 exec_output = ImmExecute.subst(iop)
414}};
415
416def format JOp(code, *opt_flags) {{
417 imm_code = """
418 imm |= UJIMMBITS19TO12 << 12;
419 imm |= UJIMMBIT11 << 11;
420 imm |= UJIMMBITS10TO1 << 1;
421 if (IMMSIGN > 0)
422 imm |= ~((uint64_t)0xFFFFF);
423 """
424 pc = 'pc.set(pc.pc() + imm);'
425 regs = ['_destRegIdx[0]']
267 {'code': code, 'imm_code': imm_code,
268 'regs': ','.join(regs)}, opt_flags)
269 header_output = ImmDeclare.subst(iop)
270 decoder_output = ImmConstructor.subst(iop)
271 decode_block = BasicDecode.subst(iop)
272 exec_output = ImmExecute.subst(iop)
273}};
274
275def format JOp(code, *opt_flags) {{
276 imm_code = """
277 imm |= UJIMMBITS19TO12 << 12;
278 imm |= UJIMMBIT11 << 11;
279 imm |= UJIMMBITS10TO1 << 1;
280 if (IMMSIGN > 0)
281 imm |= ~((uint64_t)0xFFFFF);
282 """
283 pc = 'pc.set(pc.pc() + imm);'
284 regs = ['_destRegIdx[0]']
426 iop = InstObjParams(name, Name, 'BranchOp',
285 iop = InstObjParams(name, Name, 'ImmOp<int64_t>',
427 {'code': code, 'imm_code': imm_code,
428 'regs': ','.join(regs)}, opt_flags)
429 header_output = BranchDeclare.subst(iop)
430 decoder_output = ImmConstructor.subst(iop)
431 decode_block = BasicDecode.subst(iop)
432 exec_output = BranchExecute.subst(iop)
433}};
434

--- 15 unchanged lines hidden --- 		286 {'code': code, 'imm_code': imm_code,
287 'regs': ','.join(regs)}, opt_flags)
288 header_output = BranchDeclare.subst(iop)
289 decoder_output = ImmConstructor.subst(iop)
290 decode_block = BasicDecode.subst(iop)
291 exec_output = BranchExecute.subst(iop)
292}};
293

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