standard.isa (12234:78ece221f9f5) standard.isa (12236:126ac9da6050)
1// -*- mode:c++ -*-
2
3// Copyright (c) 2015 RISC-V Foundation
4// Copyright (c) 2016-2017 The University of Virginia
5// All rights reserved.
6//
7// Redistribution and use in source and binary forms, with or without
8// modification, are permitted provided that the following conditions are

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179 //
180 // Static instruction class for "%(mnemonic)s".
181 //
182 class %(class_name)s : public %(base_class)s
183 {
184 public:
185 /// Constructor.
186 %(class_name)s(MachInst machInst);
1// -*- mode:c++ -*-
2
3// Copyright (c) 2015 RISC-V Foundation
4// Copyright (c) 2016-2017 The University of Virginia
5// All rights reserved.
6//
7// Redistribution and use in source and binary forms, with or without
8// modification, are permitted provided that the following conditions are

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179 //
180 // Static instruction class for "%(mnemonic)s".
181 //
182 class %(class_name)s : public %(base_class)s
183 {
184 public:
185 /// Constructor.
186 %(class_name)s(MachInst machInst);
187 %(BasicExecDeclare)s
187 Fault execute(ExecContext *, Trace::InstRecord *) const;
188 std::string generateDisassembly(Addr pc,
189 const SymbolTable *symtab) const override;
190 };
191}};
192
193def template ImmConstructor {{
194 %(class_name)s::%(class_name)s(MachInst machInst)
195 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s)

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235 //
236 // Static instruction class for "%(mnemonic)s".
237 //
238 class %(class_name)s : public %(base_class)s
239 {
240 public:
241 /// Constructor.
242 %(class_name)s(MachInst machInst);
188 std::string generateDisassembly(Addr pc,
189 const SymbolTable *symtab) const override;
190 };
191}};
192
193def template ImmConstructor {{
194 %(class_name)s::%(class_name)s(MachInst machInst)
195 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s)

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235 //
236 // Static instruction class for "%(mnemonic)s".
237 //
238 class %(class_name)s : public %(base_class)s
239 {
240 public:
241 /// Constructor.
242 %(class_name)s(MachInst machInst);
243 %(BasicExecDeclare)s
243 Fault execute(ExecContext *, Trace::InstRecord *) const;
244
245 std::string
246 generateDisassembly(Addr pc, const SymbolTable *symtab) const override;
247
248 RiscvISA::PCState
249 branchTarget(const RiscvISA::PCState &branchPC) const override;
250
251 using StaticInst::branchTarget;

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294 //
295 // Static instruction class for "%(mnemonic)s".
296 //
297 class %(class_name)s : public %(base_class)s
298 {
299 public:
300 /// Constructor.
301 %(class_name)s(MachInst machInst);
244
245 std::string
246 generateDisassembly(Addr pc, const SymbolTable *symtab) const override;
247
248 RiscvISA::PCState
249 branchTarget(const RiscvISA::PCState &branchPC) const override;
250
251 using StaticInst::branchTarget;

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294 //
295 // Static instruction class for "%(mnemonic)s".
296 //
297 class %(class_name)s : public %(base_class)s
298 {
299 public:
300 /// Constructor.
301 %(class_name)s(MachInst machInst);
302 %(BasicExecDeclare)s
302 Fault execute(ExecContext *, Trace::InstRecord *) const;
303
304 std::string
305 generateDisassembly(Addr pc, const SymbolTable *symtab) const override;
306
307 RiscvISA::PCState
308 branchTarget(ThreadContext *tc) const override;
309
310 using StaticInst::branchTarget;

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304 std::string
305 generateDisassembly(Addr pc, const SymbolTable *symtab) const override;
306
307 RiscvISA::PCState
308 branchTarget(ThreadContext *tc) const override;
309
310 using StaticInst::branchTarget;

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