1// -*- mode:c++ -*- 2 3// Copyright (c) 2015 RISC-V Foundation 4// Copyright (c) 2016-2017 The University of Virginia 5// All rights reserved. 6// 7// Redistribution and use in source and binary forms, with or without 8// modification, are permitted provided that the following conditions are --- 187 unchanged lines hidden (view full) --- 196 { 197 %(constructor)s; 198 %(imm_code)s; 199 } 200}}; 201 202def template ImmExecute {{ 203 Fault |
204 %(class_name)s::execute( 205 ExecContext *xc, Trace::InstRecord *traceData) const |
206 { 207 Fault fault = NoFault; 208 209 %(op_decl)s; 210 %(op_rd)s; 211 if (fault == NoFault) { 212 %(code)s; 213 if (fault == NoFault) { --- 35 unchanged lines hidden (view full) --- 249 branchTarget(const RiscvISA::PCState &branchPC) const override; 250 251 using StaticInst::branchTarget; 252 }; 253}}; 254 255def template BranchExecute {{ 256 Fault |
257 %(class_name)s::execute(ExecContext *xc, |
258 Trace::InstRecord *traceData) const 259 { 260 Fault fault = NoFault; 261 262 %(op_decl)s; 263 %(op_rd)s; 264 if (fault == NoFault) { 265 %(code)s; --- 42 unchanged lines hidden (view full) --- 308 branchTarget(ThreadContext *tc) const override; 309 310 using StaticInst::branchTarget; 311 }; 312}}; 313 314def template JumpExecute {{ 315 Fault |
316 %(class_name)s::execute( 317 ExecContext *xc, Trace::InstRecord *traceData) const |
318 { 319 Fault fault = NoFault; 320 321 %(op_decl)s; 322 %(op_rd)s; 323 if (fault == NoFault) { 324 %(code)s; 325 if (fault == NoFault) { --- 124 unchanged lines hidden --- |