36,46d35
< output header {{
< /**
< * Base class for operations that work only on registers
< */
< class RegOp : public RiscvStaticInst
< {
< protected:
< /// Constructor
< RegOp(const char *mnem, MachInst _machInst, OpClass __opClass)
< : RiscvStaticInst(mnem, _machInst, __opClass)
< {}
48,177d36
< std::string
< generateDisassembly(Addr pc, const SymbolTable *symtab) const;
< };
<
< /**
< * Base class for operations with signed immediates
< */
< class ImmOp : public RiscvStaticInst
< {
< protected:
< int64_t imm;
<
< /// Constructor
< ImmOp(const char *mnem, MachInst _machInst, OpClass __opClass)
< : RiscvStaticInst(mnem, _machInst, __opClass), imm(0)
< {}
<
< virtual std::string
< generateDisassembly(Addr pc, const SymbolTable *symtab) const = 0;
< };
<
< /**
< * Base class for operations with unsigned immediates
< */
< class UImmOp : public RiscvStaticInst
< {
< protected:
< uint64_t imm;
<
< /// Constructor
< UImmOp(const char *mnem, MachInst _machInst, OpClass __opClass)
< : RiscvStaticInst(mnem, _machInst, __opClass), imm(0)
< {}
<
< virtual std::string
< generateDisassembly(Addr pc, const SymbolTable *symtab) const = 0;
< };
<
< /**
< * Base class for operations with branching
< */
< class BranchOp : public ImmOp
< {
< protected:
< /// Constructor
< BranchOp(const char *mnem, MachInst _machInst, OpClass __opClass)
< : ImmOp(mnem, _machInst, __opClass)
< {}
<
< using StaticInst::branchTarget;
<
< virtual RiscvISA::PCState
< branchTarget(ThreadContext *tc) const
< {
< return StaticInst::branchTarget(tc);
< }
<
< virtual RiscvISA::PCState
< branchTarget(const RiscvISA::PCState &branchPC) const
< {
< return StaticInst::branchTarget(branchPC);
< }
<
< virtual std::string
< generateDisassembly(Addr pc, const SymbolTable *symtab) const = 0;
< };
<
< /**
< * Base class for system operations
< */
< class SystemOp : public RiscvStaticInst
< {
< public:
< /// Constructor
< SystemOp(const char *mnem, MachInst _machInst, OpClass __opClass)
< : RiscvStaticInst(mnem, _machInst, __opClass)
< {}
<
< std::string
< generateDisassembly(Addr pc, const SymbolTable *symtab) const
< {
< return mnemonic;
< }
< };
<
< /**
< * Base class for CSR operations
< */
< class CSROp : public RiscvStaticInst
< {
< protected:
< uint64_t csr;
< uint64_t uimm;
<
< public:
< /// Constructor
< CSROp(const char *mnem, MachInst _machInst, OpClass __opClass)
< : RiscvStaticInst(mnem, _machInst, __opClass),
< csr(FUNCT12), uimm(CSRIMM)
< {}
<
< std::string
< generateDisassembly(Addr pc, const SymbolTable *symtab) const;
< };
< }};
<
< //Outputs to decoder.cc
< output decoder {{
< std::string
< RegOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
< {
< std::stringstream ss;
< ss << mnemonic << ' ' << registerName(_destRegIdx[0]) << ", " <<
< registerName(_srcRegIdx[0]) << ", " <<
< registerName(_srcRegIdx[1]);
< return ss.str();
< }
<
< std::string
< CSROp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
< {
< std::stringstream ss;
< ss << mnemonic << ' ' << registerName(_destRegIdx[0]) << ", ";
< if (_numSrcRegs > 0)
< ss << registerName(_srcRegIdx[0]) << ", ";
< ss << MiscRegNames.at(csr);
< return ss.str();
< }
< }};
<
365c224
< iop = InstObjParams(name, Name, 'ImmOp',
---
> iop = InstObjParams(name, Name, 'ImmOp<int64_t>',
383c242
< iop = InstObjParams(name, Name, 'BranchOp',
---
> iop = InstObjParams(name, Name, 'ImmOp<int64_t>',
395c254
< iop = InstObjParams(name, Name, 'BranchOp',
---
> iop = InstObjParams(name, Name, 'ImmOp<int64_t>',
407c266
< iop = InstObjParams(name, Name, 'ImmOp',
---
> iop = InstObjParams(name, Name, 'ImmOp<int64_t>',
426c285
< iop = InstObjParams(name, Name, 'BranchOp',
---
> iop = InstObjParams(name, Name, 'ImmOp<int64_t>',