mem.isa (12236:126ac9da6050) mem.isa (12322:e5a1d42b876b)
1// -*- mode:c++ -*-
2
3// Copyright (c) 2015 RISC-V Foundation
4// Copyright (c) 2016 The University of Virginia
5// All rights reserved.
6//
7// Redistribution and use in source and binary forms, with or without
8// modification, are permitted provided that the following conditions are

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28// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
29//
30// Authors: Alec Roelke
31
32////////////////////////////////////////////////////////////////////
33//
34// Memory operation instructions
35//
1// -*- mode:c++ -*-
2
3// Copyright (c) 2015 RISC-V Foundation
4// Copyright (c) 2016 The University of Virginia
5// All rights reserved.
6//
7// Redistribution and use in source and binary forms, with or without
8// modification, are permitted provided that the following conditions are

--- 19 unchanged lines hidden (view full) ---

28// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
29//
30// Authors: Alec Roelke
31
32////////////////////////////////////////////////////////////////////
33//
34// Memory operation instructions
35//
36output header {{
37 class Load : public RiscvStaticInst
38 {
39 public:
40 /// Displacement for EA calculation (signed).
41 int64_t ldisp;
42
43 protected:
44 /// Memory request flags. See mem_req_base.hh.
45 Request::Flags memAccessFlags;
46
47 /// Constructor
48 Load(const char *mnem, ExtMachInst _machInst, OpClass __opClass)
49 : RiscvStaticInst(mnem, _machInst, __opClass), ldisp(0)
50 {}
51
52 std::string
53 generateDisassembly(Addr pc, const SymbolTable *symtab) const;
54 };
55
56 class Store : public RiscvStaticInst
57 {
58 public:
59 /// Displacement for EA calculation (signed).
60 int64_t sdisp;
61
62 protected:
63 /// Memory request flags. See mem_req_base.hh.
64 Request::Flags memAccessFlags;
65
66 /// Constructor
67 Store(const char *mnem, ExtMachInst _machInst, OpClass __opClass)
68 : RiscvStaticInst(mnem, _machInst, __opClass), sdisp(0)
69 {
70 sdisp = IMM5 | (IMM7 << 5);
71 if (IMMSIGN > 0)
72 sdisp |= ~((uint64_t)0xFFF);
73 }
74
75 std::string
76 generateDisassembly(Addr pc, const SymbolTable *symtab) const;
77 };
78
79}};
80
81
82output decoder {{
83 std::string
84 Load::generateDisassembly(Addr pc, const SymbolTable *symtab) const
85 {
86 std::stringstream ss;
87 ss << mnemonic << ' ' << registerName(_destRegIdx[0]) << ", " <<
88 ldisp << '(' << registerName(_srcRegIdx[0]) << ')';
89 return ss.str();
90 }
91
92 std::string
93 Store::generateDisassembly(Addr pc, const SymbolTable *symtab) const
94 {
95 std::stringstream ss;
96 ss << mnemonic << ' ' << registerName(_srcRegIdx[1]) << ", " <<
97 sdisp << '(' << registerName(_srcRegIdx[0]) << ')';
98 return ss.str();
99 }
100}};
101
102def template LoadStoreDeclare {{
103 /**
104 * Static instruction class for "%(mnemonic)s".
105 */
106 class %(class_name)s : public %(base_class)s
107 {
108 public:
109 /// Constructor.

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315 Fault
316 %(class_name)s::completeAcc(PacketPtr pkt, ExecContext *xc,
317 Trace::InstRecord *traceData) const
318 {
319 return NoFault;
320 }
321}};
322
36def template LoadStoreDeclare {{
37 /**
38 * Static instruction class for "%(mnemonic)s".
39 */
40 class %(class_name)s : public %(base_class)s
41 {
42 public:
43 /// Constructor.

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249 Fault
250 %(class_name)s::completeAcc(PacketPtr pkt, ExecContext *xc,
251 Trace::InstRecord *traceData) const
252 {
253 return NoFault;
254 }
255}};
256
323def format Load(memacc_code, ea_code = {{EA = Rs1 + ldisp;}}, mem_flags=[],
257def format Load(memacc_code, ea_code = {{EA = Rs1 + offset;}}, mem_flags=[],
324 inst_flags=[]) {{
325 offset_code = """
258 inst_flags=[]) {{
259 offset_code = """
326 ldisp = IMM12;
260 offset = IMM12;
327 if (IMMSIGN > 0)
261 if (IMMSIGN > 0)
328 ldisp |= ~((uint64_t)0xFFF);
262 offset |= ~((uint64_t)0xFFF);
329 """
330 (header_output, decoder_output, decode_block, exec_output) = \
331 LoadStoreBase(name, Name, offset_code, ea_code, memacc_code, mem_flags,
332 inst_flags, 'Load', exec_template_base='Load')
333}};
334
263 """
264 (header_output, decoder_output, decode_block, exec_output) = \
265 LoadStoreBase(name, Name, offset_code, ea_code, memacc_code, mem_flags,
266 inst_flags, 'Load', exec_template_base='Load')
267}};
268
335def format Store(memacc_code, ea_code={{EA = Rs1 + sdisp;}}, mem_flags=[],
269def format Store(memacc_code, ea_code={{EA = Rs1 + offset;}}, mem_flags=[],
336 inst_flags=[]) {{
337 offset_code = """
270 inst_flags=[]) {{
271 offset_code = """
338 sdisp = IMM5 | (IMM7 << 5);
272 offset = IMM5 | (IMM7 << 5);
339 if (IMMSIGN > 0)
273 if (IMMSIGN > 0)
340 sdisp |= ~((uint64_t)0xFFF);
274 offset |= ~((uint64_t)0xFFF);
341 """
342 (header_output, decoder_output, decode_block, exec_output) = \
343 LoadStoreBase(name, Name, offset_code, ea_code, memacc_code, mem_flags,
344 inst_flags, 'Store', exec_template_base='Store')
345}};
275 """
276 (header_output, decoder_output, decode_block, exec_output) = \
277 LoadStoreBase(name, Name, offset_code, ea_code, memacc_code, mem_flags,
278 inst_flags, 'Store', exec_template_base='Store')
279}};