mem.isa (12119:e9ef3ee3171d) mem.isa (12120:133620bfc43b)
1// -*- mode:c++ -*-
2
3// Copyright (c) 2015 RISC-V Foundation
4// Copyright (c) 2016 The University of Virginia
5// All rights reserved.
6//
7// Redistribution and use in source and binary forms, with or without
8// modification, are permitted provided that the following conditions are

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41 int64_t ldisp;
42
43 protected:
44 /// Memory request flags. See mem_req_base.hh.
45 Request::Flags memAccessFlags;
46
47 /// Constructor
48 Load(const char *mnem, ExtMachInst _machInst, OpClass __opClass)
1// -*- mode:c++ -*-
2
3// Copyright (c) 2015 RISC-V Foundation
4// Copyright (c) 2016 The University of Virginia
5// All rights reserved.
6//
7// Redistribution and use in source and binary forms, with or without
8// modification, are permitted provided that the following conditions are

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41 int64_t ldisp;
42
43 protected:
44 /// Memory request flags. See mem_req_base.hh.
45 Request::Flags memAccessFlags;
46
47 /// Constructor
48 Load(const char *mnem, ExtMachInst _machInst, OpClass __opClass)
49 : RiscvStaticInst(mnem, _machInst, __opClass), ldisp(IMM12)
50 {
51 if (IMMSIGN > 0)
52 ldisp |= ~((uint64_t)0xFFF);
53 }
49 : RiscvStaticInst(mnem, _machInst, __opClass), ldisp(0)
50 {}
54
55 std::string
56 generateDisassembly(Addr pc, const SymbolTable *symtab) const;
57 };
58
59 class Store : public RiscvStaticInst
60 {
61 public:
62 /// Displacement for EA calculation (signed).
63 int64_t sdisp;
64
65 protected:
66 /// Memory request flags. See mem_req_base.hh.
67 Request::Flags memAccessFlags;
68
69 /// Constructor
70 Store(const char *mnem, ExtMachInst _machInst, OpClass __opClass)
51
52 std::string
53 generateDisassembly(Addr pc, const SymbolTable *symtab) const;
54 };
55
56 class Store : public RiscvStaticInst
57 {
58 public:
59 /// Displacement for EA calculation (signed).
60 int64_t sdisp;
61
62 protected:
63 /// Memory request flags. See mem_req_base.hh.
64 Request::Flags memAccessFlags;
65
66 /// Constructor
67 Store(const char *mnem, ExtMachInst _machInst, OpClass __opClass)
71 : RiscvStaticInst(mnem, _machInst, __opClass), sdisp(IMM5)
68 : RiscvStaticInst(mnem, _machInst, __opClass), sdisp(0)
72 {
69 {
73 sdisp |= IMM7 << 5;
70 sdisp = IMM5 | (IMM7 << 5);
74 if (IMMSIGN > 0)
75 sdisp |= ~((uint64_t)0xFFF);
76 }
77
78 std::string
79 generateDisassembly(Addr pc, const SymbolTable *symtab) const;
80 };
81

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138 completeAcc(PacketPtr, %(CPU_exec_context)s *, Trace::InstRecord *) const;
139}};
140
141def template LoadStoreConstructor {{
142 %(class_name)s::%(class_name)s(ExtMachInst machInst):
143 %(base_class)s("%(mnemonic)s", machInst, %(op_class)s)
144 {
145 %(constructor)s;
71 if (IMMSIGN > 0)
72 sdisp |= ~((uint64_t)0xFFF);
73 }
74
75 std::string
76 generateDisassembly(Addr pc, const SymbolTable *symtab) const;
77 };
78

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135 completeAcc(PacketPtr, %(CPU_exec_context)s *, Trace::InstRecord *) const;
136}};
137
138def template LoadStoreConstructor {{
139 %(class_name)s::%(class_name)s(ExtMachInst machInst):
140 %(base_class)s("%(mnemonic)s", machInst, %(op_class)s)
141 {
142 %(constructor)s;
143 %(offset_code)s;
146 }
147}};
148
149def template EACompExecute {{
150 Fault
151 %(class_name)s::eaComp(CPU_EXEC_CONTEXT *xc,
152 Trace::InstRecord *traceData) const
153 {

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163 xc->setEA(EA);
164 }
165
166 return fault;
167 }
168}};
169
170let {{
144 }
145}};
146
147def template EACompExecute {{
148 Fault
149 %(class_name)s::eaComp(CPU_EXEC_CONTEXT *xc,
150 Trace::InstRecord *traceData) const
151 {

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161 xc->setEA(EA);
162 }
163
164 return fault;
165 }
166}};
167
168let {{
171def LoadStoreBase(name, Name, ea_code, memacc_code, mem_flags, inst_flags,
172 base_class, postacc_code='', decode_template=BasicDecode,
169def LoadStoreBase(name, Name, offset_code, ea_code, memacc_code, mem_flags,
170 inst_flags, base_class, postacc_code='', decode_template=BasicDecode,
173 exec_template_base=''):
174 # Make sure flags are in lists (convert to lists if not).
175 mem_flags = makeList(mem_flags)
171 exec_template_base=''):
172 # Make sure flags are in lists (convert to lists if not).
173 mem_flags = makeList(mem_flags)
176 inst_flags = makeList(inst_flags) # + ['IsNonSpeculative']
174 inst_flags = makeList(inst_flags)
177
178 iop = InstObjParams(name, Name, base_class,
175
176 iop = InstObjParams(name, Name, base_class,
179 { 'ea_code':ea_code, 'memacc_code':memacc_code,
180 'postacc_code':postacc_code }, inst_flags)
177 {'offset_code': offset_code, 'ea_code': ea_code,
178 'memacc_code': memacc_code, 'postacc_code': postacc_code },
179 inst_flags)
181
182 if mem_flags:
183 mem_flags = [ 'Request::%s' % flag for flag in mem_flags ]
184 s = '\n\tmemAccessFlags = ' + string.join(mem_flags, '|') + ';'
185 iop.constructor += s
186
187 # select templates
188

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337 Trace::InstRecord *traceData) const
338 {
339 return NoFault;
340 }
341}};
342
343def format Load(memacc_code, ea_code = {{EA = Rs1 + ldisp;}}, mem_flags=[],
344 inst_flags=[]) {{
180
181 if mem_flags:
182 mem_flags = [ 'Request::%s' % flag for flag in mem_flags ]
183 s = '\n\tmemAccessFlags = ' + string.join(mem_flags, '|') + ';'
184 iop.constructor += s
185
186 # select templates
187

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336 Trace::InstRecord *traceData) const
337 {
338 return NoFault;
339 }
340}};
341
342def format Load(memacc_code, ea_code = {{EA = Rs1 + ldisp;}}, mem_flags=[],
343 inst_flags=[]) {{
344 offset_code = """
345 ldisp = IMM12;
346 if (IMMSIGN > 0)
347 ldisp |= ~((uint64_t)0xFFF);
348 """
345 (header_output, decoder_output, decode_block, exec_output) = \
349 (header_output, decoder_output, decode_block, exec_output) = \
346 LoadStoreBase(name, Name, ea_code, memacc_code, mem_flags, inst_flags,
347 'Load', exec_template_base='Load')
350 LoadStoreBase(name, Name, offset_code, ea_code, memacc_code, mem_flags,
351 inst_flags, 'Load', exec_template_base='Load')
348}};
349
350def format Store(memacc_code, ea_code={{EA = Rs1 + sdisp;}}, mem_flags=[],
351 inst_flags=[]) {{
352}};
353
354def format Store(memacc_code, ea_code={{EA = Rs1 + sdisp;}}, mem_flags=[],
355 inst_flags=[]) {{
356 offset_code = """
357 sdisp = IMM5 | (IMM7 << 5);
358 if (IMMSIGN > 0)
359 sdisp |= ~((uint64_t)0xFFF);
360 """
352 (header_output, decoder_output, decode_block, exec_output) = \
361 (header_output, decoder_output, decode_block, exec_output) = \
353 LoadStoreBase(name, Name, ea_code, memacc_code, mem_flags, inst_flags,
354 'Store', exec_template_base='Store')
362 LoadStoreBase(name, Name, offset_code, ea_code, memacc_code, mem_flags,
363 inst_flags, 'Store', exec_template_base='Store')
355}};
364}};