mem.isa (11729:f37b5fcd66fe) mem.isa (11965:41e942451f59)
1// -*- mode:c++ -*-
2
3// Copyright (c) 2015 RISC-V Foundation
4// Copyright (c) 2016 The University of Virginia
5// All rights reserved.
6//
7// Redistribution and use in source and binary forms, with or without
8// modification, are permitted provided that the following conditions are

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181
182 if mem_flags:
183 mem_flags = [ 'Request::%s' % flag for flag in mem_flags ]
184 s = '\n\tmemAccessFlags = ' + string.join(mem_flags, '|') + ';'
185 iop.constructor += s
186
187 # select templates
188
1// -*- mode:c++ -*-
2
3// Copyright (c) 2015 RISC-V Foundation
4// Copyright (c) 2016 The University of Virginia
5// All rights reserved.
6//
7// Redistribution and use in source and binary forms, with or without
8// modification, are permitted provided that the following conditions are

--- 172 unchanged lines hidden (view full) ---

181
182 if mem_flags:
183 mem_flags = [ 'Request::%s' % flag for flag in mem_flags ]
184 s = '\n\tmemAccessFlags = ' + string.join(mem_flags, '|') + ';'
185 iop.constructor += s
186
187 # select templates
188
189 # The InitiateAcc template is the same for StoreCond templates as the
190 # corresponding Store template..
191 StoreCondInitiateAcc = StoreInitiateAcc
192
193 fullExecTemplate = eval(exec_template_base + 'Execute')
194 initiateAccTemplate = eval(exec_template_base + 'InitiateAcc')
195 completeAccTemplate = eval(exec_template_base + 'CompleteAcc')
196
197 # (header_output, decoder_output, decode_block, exec_output)
198 return (LoadStoreDeclare.subst(iop),
199 LoadStoreConstructor.subst(iop),
200 decode_template.subst(iop),

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339 Fault
340 %(class_name)s::completeAcc(PacketPtr pkt, CPU_EXEC_CONTEXT *xc,
341 Trace::InstRecord *traceData) const
342 {
343 return NoFault;
344 }
345}};
346
189 fullExecTemplate = eval(exec_template_base + 'Execute')
190 initiateAccTemplate = eval(exec_template_base + 'InitiateAcc')
191 completeAccTemplate = eval(exec_template_base + 'CompleteAcc')
192
193 # (header_output, decoder_output, decode_block, exec_output)
194 return (LoadStoreDeclare.subst(iop),
195 LoadStoreConstructor.subst(iop),
196 decode_template.subst(iop),

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335 Fault
336 %(class_name)s::completeAcc(PacketPtr pkt, CPU_EXEC_CONTEXT *xc,
337 Trace::InstRecord *traceData) const
338 {
339 return NoFault;
340 }
341}};
342
347def template StoreCondExecute {{
348 Fault %(class_name)s::execute(CPU_EXEC_CONTEXT *xc,
349 Trace::InstRecord *traceData) const
350 {
351 Addr EA;
352 Fault fault = NoFault;
353 uint64_t result;
354
355 %(op_decl)s;
356 %(op_rd)s;
357 %(ea_code)s;
358
359 if (fault == NoFault) {
360 %(memacc_code)s;
361 }
362
363 if (fault == NoFault) {
364 fault = writeMemAtomic(xc, traceData, Mem, EA, memAccessFlags,
365 &result);
366 // RISC-V has the opposite convention gem5 has for success flags,
367 // so we invert the result here.
368 result = !result;
369 }
370
371 if (fault == NoFault) {
372 %(postacc_code)s;
373 }
374
375 if (fault == NoFault) {
376 %(op_wb)s;
377 }
378
379 return fault;
380 }
381}};
382
383def template StoreCondCompleteAcc {{
384 Fault %(class_name)s::completeAcc(Packet *pkt, CPU_EXEC_CONTEXT *xc,
385 Trace::InstRecord *traceData) const
386 {
387 Fault fault = NoFault;
388
389 %(op_dest_decl)s;
390
391 // RISC-V has the opposite convention gem5 has for success flags,
392 // so we invert the result here.
393 uint64_t result = !pkt->req->getExtraData();
394
395 if (fault == NoFault) {
396 %(postacc_code)s;
397 }
398
399 if (fault == NoFault) {
400 %(op_wb)s;
401 }
402
403 return fault;
404 }
405}};
406
407def format Load(memacc_code, ea_code = {{EA = Rs1 + ldisp;}}, mem_flags=[],
408 inst_flags=[]) {{
409 (header_output, decoder_output, decode_block, exec_output) = \
410 LoadStoreBase(name, Name, ea_code, memacc_code, mem_flags, inst_flags,
411 'Load', exec_template_base='Load')
412}};
413
414def format Store(memacc_code, ea_code={{EA = Rs1 + sdisp;}}, mem_flags=[],
415 inst_flags=[]) {{
416 (header_output, decoder_output, decode_block, exec_output) = \
417 LoadStoreBase(name, Name, ea_code, memacc_code, mem_flags, inst_flags,
418 'Store', exec_template_base='Store')
419}};
343def format Load(memacc_code, ea_code = {{EA = Rs1 + ldisp;}}, mem_flags=[],
344 inst_flags=[]) {{
345 (header_output, decoder_output, decode_block, exec_output) = \
346 LoadStoreBase(name, Name, ea_code, memacc_code, mem_flags, inst_flags,
347 'Load', exec_template_base='Load')
348}};
349
350def format Store(memacc_code, ea_code={{EA = Rs1 + sdisp;}}, mem_flags=[],
351 inst_flags=[]) {{
352 (header_output, decoder_output, decode_block, exec_output) = \
353 LoadStoreBase(name, Name, ea_code, memacc_code, mem_flags, inst_flags,
354 'Store', exec_template_base='Store')
355}};
420
421def format StoreCond(memacc_code, postacc_code, ea_code={{EA = Rs1;}},
422 mem_flags=[], inst_flags=[], aq=0, rl=0) {{
423 if aq:
424 mem_flags = makeList(mem_flags) + ["ACQUIRE"]
425 if rl:
426 mem_flags = makeList(mem_flags) + ["RELEASE"]
427 (header_output, decoder_output, decode_block, exec_output) = LoadStoreBase(
428 name, Name, ea_code, memacc_code, mem_flags, inst_flags, 'Store',
429 postacc_code, exec_template_base='StoreCond')
430}};
431
432def format LoadReserved(memacc_code, ea_code={{EA = Rs1;}}, mem_flags=[],
433 inst_flags=[], aq=0, rl=0) {{
434 if aq:
435 mem_flags = makeList(mem_flags) + ["ACQUIRE"]
436 if rl:
437 mem_flags = makeList(mem_flags) + ["RELEASE"]
438 (header_output, decoder_output, decode_block, exec_output) = LoadStoreBase(
439 name, Name, ea_code, memacc_code, mem_flags, inst_flags, 'Load',
440 exec_template_base='Load')
441}};