1// -*- mode:c++ -*- 2 3// Copyright (c) 2015 RISC-V Foundation 4// Copyright (c) 2016 The University of Virginia 5// All rights reserved. 6// 7// Redistribution and use in source and binary forms, with or without 8// modification, are permitted provided that the following conditions are --- 240 unchanged lines hidden (view full) --- 249 Fault 250 %(class_name)s::completeAcc(PacketPtr pkt, ExecContext *xc, 251 Trace::InstRecord *traceData) const 252 { 253 return NoFault; 254 } 255}}; 256 |
257def format Load(memacc_code, ea_code = {{EA = Rs1 + offset;}}, 258 offset_code={{offset = sext<12>(IMM12);}}, 259 mem_flags=[], inst_flags=[]) {{ |
260 (header_output, decoder_output, decode_block, exec_output) = \ 261 LoadStoreBase(name, Name, offset_code, ea_code, memacc_code, mem_flags, 262 inst_flags, 'Load', exec_template_base='Load') 263}}; 264 |
265def format Store(memacc_code, ea_code={{EA = Rs1 + offset;}}, 266 offset_code={{offset = sext<12>(IMM5 | (IMM7 << 5));}}, 267 mem_flags=[], inst_flags=[]) {{ |
268 (header_output, decoder_output, decode_block, exec_output) = \ 269 LoadStoreBase(name, Name, offset_code, ea_code, memacc_code, mem_flags, 270 inst_flags, 'Store', exec_template_base='Store') 271}}; |