36,101d35
< output header {{
< class Load : public RiscvStaticInst
< {
< public:
< /// Displacement for EA calculation (signed).
< int64_t ldisp;
<
< protected:
< /// Memory request flags. See mem_req_base.hh.
< Request::Flags memAccessFlags;
<
< /// Constructor
< Load(const char *mnem, ExtMachInst _machInst, OpClass __opClass)
< : RiscvStaticInst(mnem, _machInst, __opClass), ldisp(0)
< {}
<
< std::string
< generateDisassembly(Addr pc, const SymbolTable *symtab) const;
< };
<
< class Store : public RiscvStaticInst
< {
< public:
< /// Displacement for EA calculation (signed).
< int64_t sdisp;
<
< protected:
< /// Memory request flags. See mem_req_base.hh.
< Request::Flags memAccessFlags;
<
< /// Constructor
< Store(const char *mnem, ExtMachInst _machInst, OpClass __opClass)
< : RiscvStaticInst(mnem, _machInst, __opClass), sdisp(0)
< {
< sdisp = IMM5 | (IMM7 << 5);
< if (IMMSIGN > 0)
< sdisp |= ~((uint64_t)0xFFF);
< }
<
< std::string
< generateDisassembly(Addr pc, const SymbolTable *symtab) const;
< };
<
< }};
<
<
< output decoder {{
< std::string
< Load::generateDisassembly(Addr pc, const SymbolTable *symtab) const
< {
< std::stringstream ss;
< ss << mnemonic << ' ' << registerName(_destRegIdx[0]) << ", " <<
< ldisp << '(' << registerName(_srcRegIdx[0]) << ')';
< return ss.str();
< }
<
< std::string
< Store::generateDisassembly(Addr pc, const SymbolTable *symtab) const
< {
< std::stringstream ss;
< ss << mnemonic << ' ' << registerName(_srcRegIdx[1]) << ", " <<
< sdisp << '(' << registerName(_srcRegIdx[0]) << ')';
< return ss.str();
< }
< }};
<
323c257
< def format Load(memacc_code, ea_code = {{EA = Rs1 + ldisp;}}, mem_flags=[],
---
> def format Load(memacc_code, ea_code = {{EA = Rs1 + offset;}}, mem_flags=[],
326c260
< ldisp = IMM12;
---
> offset = IMM12;
328c262
< ldisp |= ~((uint64_t)0xFFF);
---
> offset |= ~((uint64_t)0xFFF);
335c269
< def format Store(memacc_code, ea_code={{EA = Rs1 + sdisp;}}, mem_flags=[],
---
> def format Store(memacc_code, ea_code={{EA = Rs1 + offset;}}, mem_flags=[],
338c272
< sdisp = IMM5 | (IMM7 << 5);
---
> offset = IMM5 | (IMM7 << 5);
340c274
< sdisp |= ~((uint64_t)0xFFF);
---
> offset |= ~((uint64_t)0xFFF);