1// -*- mode:c++ -*-
2
3// Copyright (c) 2015 RISC-V Foundation
4// Copyright (c) 2016 The University of Virginia
5// All rights reserved.
6//
7// Redistribution and use in source and binary forms, with or without
8// modification, are permitted provided that the following conditions are

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249 Fault
250 %(class_name)s::completeAcc(PacketPtr pkt, ExecContext *xc,
251 Trace::InstRecord *traceData) const
252 {
253 return NoFault;
254 }
255}};
256
257def format Load(memacc_code, ea_code={{EA = Rs1 + offset;}}, mem_flags=[],
258 inst_flags=[]) {{
259 offset_code = """
260 offset = IMM12;
261 if (IMMSIGN > 0)
262 offset |= ~((uint64_t)0xFFF);
263 """
264 (header_output, decoder_output, decode_block, exec_output) = \
265 LoadStoreBase(name, Name, offset_code, ea_code, memacc_code, mem_flags,
266 inst_flags, 'Load', exec_template_base='Load')
267}};
268
269def format Store(memacc_code, ea_code={{EA = Rs1 + offset;}}, mem_flags=[],
270 inst_flags=[]) {{
271 offset_code = """
272 offset = IMM5 | (IMM7 << 5);
273 if (IMMSIGN > 0)
274 offset |= ~((uint64_t)0xFFF);
275 """
276 (header_output, decoder_output, decode_block, exec_output) = \
277 LoadStoreBase(name, Name, offset_code, ea_code, memacc_code, mem_flags,
278 inst_flags, 'Store', exec_template_base='Store')
279}};