1// -*- mode:c++ -*-
2
3// Copyright (c) 2015 RISC-V Foundation
4// Copyright (c) 2016 The University of Virginia
5// All rights reserved.
6//
7// Redistribution and use in source and binary forms, with or without
8// modification, are permitted provided that the following conditions are

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116 %(InitiateAccDeclare)s
117
118 %(CompleteAccDeclare)s
119 };
120}};
121
122def template EACompDeclare {{
123 Fault
124 eaComp(%(CPU_exec_context)s *, Trace::InstRecord *) const;
125}};
126
127def template InitiateAccDeclare {{
128 Fault
129 initiateAcc(%(CPU_exec_context)s *, Trace::InstRecord *) const;
130}};
131
132
133def template CompleteAccDeclare {{
134 Fault
135 completeAcc(PacketPtr, %(CPU_exec_context)s *, Trace::InstRecord *) const;
136}};
137
138def template LoadStoreConstructor {{
139 %(class_name)s::%(class_name)s(ExtMachInst machInst):
140 %(base_class)s("%(mnemonic)s", machInst, %(op_class)s)
141 {
142 %(constructor)s;
143 %(offset_code)s;
144 }
145}};
146
147def template EACompExecute {{
148 Fault
149 %(class_name)s::eaComp(CPU_EXEC_CONTEXT *xc,
150 Trace::InstRecord *traceData) const
151 {
152 Addr EA;
153 Fault fault = NoFault;
154
155 %(op_decl)s;
156 %(op_rd)s;
157 %(ea_code)s;
158

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196 fullExecTemplate.subst(iop) +
197 EACompExecute.subst(iop) +
198 initiateAccTemplate.subst(iop) +
199 completeAccTemplate.subst(iop))
200}};
201
202def template LoadExecute {{
203 Fault
204 %(class_name)s::execute(CPU_EXEC_CONTEXT *xc,
205 Trace::InstRecord *traceData) const
206 {
207 Addr EA;
208 Fault fault = NoFault;
209
210 %(op_decl)s;
211 %(op_rd)s;
212 %(ea_code)s;
213

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221 }
222
223 return fault;
224 }
225}};
226
227def template LoadInitiateAcc {{
228 Fault
229 %(class_name)s::initiateAcc(CPU_EXEC_CONTEXT *xc,
230 Trace::InstRecord *traceData) const
231 {
232 Addr EA;
233 Fault fault = NoFault;
234
235 %(op_src_decl)s;
236 %(op_rd)s;
237 %(ea_code)s;
238
239 if (fault == NoFault) {
240 fault = initiateMemRead(xc, traceData, EA, Mem, memAccessFlags);
241 }
242
243 return fault;
244 }
245}};
246
247def template LoadCompleteAcc {{
248 Fault
249 %(class_name)s::completeAcc(PacketPtr pkt, CPU_EXEC_CONTEXT *xc,
250 Trace::InstRecord *traceData) const
251 {
252 Fault fault = NoFault;
253
254 %(op_decl)s;
255 %(op_rd)s;
256
257 getMem(pkt, Mem, traceData);

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265 }
266
267 return fault;
268 }
269}};
270
271def template StoreExecute {{
272 Fault
273 %(class_name)s::execute(CPU_EXEC_CONTEXT *xc,
274 Trace::InstRecord *traceData) const
275 {
276 Addr EA;
277 Fault fault = NoFault;
278
279 %(op_decl)s;
280 %(op_rd)s;
281 %(ea_code)s;

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298 }
299
300 return fault;
301 }
302}};
303
304def template StoreInitiateAcc {{
305 Fault
306 %(class_name)s::initiateAcc(CPU_EXEC_CONTEXT *xc,
307 Trace::InstRecord *traceData) const
308 {
309 Addr EA;
310 Fault fault = NoFault;
311
312 %(op_decl)s;
313 %(op_rd)s;
314 %(ea_code)s;

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327 }
328
329 return fault;
330 }
331}};
332
333def template StoreCompleteAcc {{
334 Fault
335 %(class_name)s::completeAcc(PacketPtr pkt, CPU_EXEC_CONTEXT *xc,
336 Trace::InstRecord *traceData) const
337 {
338 return NoFault;
339 }
340}};
341
342def format Load(memacc_code, ea_code = {{EA = Rs1 + ldisp;}}, mem_flags=[],
343 inst_flags=[]) {{

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